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PostPosted: Tue Jan 23, 2018 11:29 pm 
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Does any have, or know where the interwebs has, a timing diagram for PPU read and write cycles? Or a thorough description thereof?


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PostPosted: Wed Jan 24, 2018 12:28 am 
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https://wiki.nesdev.com/w/index.php/Fil ... timing.png


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PostPosted: Wed Jan 24, 2018 8:23 am 
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Thanks, lidnariq, but I am looking for the memory read and write cycle timing diagrams like one would find in a datasheet with setup and hold times, etc.


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PostPosted: Wed Jan 24, 2018 10:44 am 
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No setup and hold times for you.

That diagram actually does indicate the timing of the PPU's address and data buses during rendering: during every pixel either the data bus is driven with the lowest 8 bits of the address and ALE is asserted, or the data bus is floating and /RD is asserted.


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PostPosted: Wed Jan 24, 2018 12:10 pm 
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I think plainsteve wants it down to the sixteen half-periods of the master clock that make up each pixel. This would be useful to figure out the timing constraints on memories that interoperate with the PPU, particularly the time between when the PPU expects the value to have settled on the data bus and when the PPU drives the next low address onto the data bus.


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PostPosted: Wed Jan 24, 2018 12:18 pm 
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If he wants setup and hold times, he's asking about analog properties of the silicon process that we don't have.


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PostPosted: Wed Jan 24, 2018 2:09 pm 
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Quote:
I think plainsteve wants it down to the sixteen half-periods of the master clock that make up each pixel.


That would be nice. Setup and hold times per se aren't too important, but other timing information (like what a datasheet would have) would be helpful. For example, after the PPU drives /RD low to indicate a RD, when is the data bus actually sampled? When is /RD released?

I was hoping, if there was no datasheet, that someone in the past had logged this info from a logic analyzer (LA) or some such. (I do not have a LA.)

Thanks!


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PostPosted: Wed Jan 24, 2018 2:14 pm 
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http://www.qmtpro.com/~nes/chipimages/visual2c02/
it's not exactly a datasheet, but it does let you inspect everything on a microtick-by-microtick basis.

Almost everything just runs on the pixel clock.


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PostPosted: Wed Jan 24, 2018 5:06 pm 
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Thanks, lidnariq!

Each PPU memory access takes 2 PPU cycles.

From Visual2C02, it looks like PPU ALE signal goes active (high) during the first HALF of the first cycle of a memory read.
(This contradicts the information at https://wiki.nesdev.com/w/index.php/PPU_pin_out_and_signal_description, which says it says high for one cycle.)

Then, PPU /RD goes active (low) for the entirety of the second cycle.

I don't know how to stimulate Visual2C02 to do a write cycle. Any ideas?


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PostPosted: Wed Jan 24, 2018 5:14 pm 
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That cryptic column in the middle of the upper-right pane:
- * + W 0 ff &c
I could have sworn I used to see a link to documentation but...

- is "remove this row"
* is "set evaluation pointer here"
+ is "add a row after here"
W is "CPU interface is Read / Write / -idle"
0 is the value asserted on AB0-AB2 (i.e. PPU register $2000-$2007)
ff is the value written to DB0-DB7or is filled with the value read from

Each row runs on standard NTSC 2A03G timing: io_ce is high for 9 half-master-clocks and asserted low if the 4th column isn't "-" for 15 half-master-clocks.

Also note that the timing for reads during rendering aren't necessarily the same as CPU-triggered ones.


Last edited by lidnariq on Wed Jan 24, 2018 5:24 pm, edited 1 time in total.

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PostPosted: Wed Jan 24, 2018 5:23 pm 
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So, there is a way to stimulate CPU write but what about PPU write (to video memory)?


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PostPosted: Wed Jan 24, 2018 5:25 pm 
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Like in hardware, only by the CPU asking the PPU to engage in a write cycle.


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PostPosted: Wed Jan 24, 2018 5:38 pm 
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Oh, of course. Thanks a lot!


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