Your results may vary with the software, but here's a basic breakdown of my experiences with the softwares and current devices being offered.Bregalad wrote:I use this at work and I don't have any problem, is it worse than Xilinx or Altera tools which are also very user un-friendly ?infiniteneslives wrote:All that said, Lattice's lever classic isn't user friendly by any stretch so I have a hard time recommending the LC4032V for that reason, but it gets the job done.
Xilinx ISE: Very stable, I've never had it fail to work as expected in synthesis without giving a meaningful error/warning. Editing pinouts via .ucf text file is very easy and pain free. IMO ISE is great especially if you're learning to use CPLDs, but unfortunately Xilinx no longer has 5v tolerant CPLDs recommended for new designs. ISE is the only software that supports legacy devices such as the powerpak's FPGA.
Xilinx Vivado: I tried it when it first came out a few years back and ISE recommended I migrate from ISE. I didn't feel like going through the annoyance of translating 30 some projects over especially because .ucf files didn't seem to be supported for pinout assignments. If you're starting fresh, hopefully vivado is just as good as ISE if not better.
Xilinx 5v tolerant devices:
3 years ago they announced EOL on the xc9500xl series & discontinued PLCC packages. VQFP packages are still available, but the prices were raised with the EOL announcement and their days are numbered. I wouldn't be surprised to see the entire xc9500xl line get the axe this year, but who knows..
Xilinx 3v only devices:
Coolrunner and older Spartan series are in the same boat as xc9500xl (see discontinuation notice). It doesn't matter much though, of the older Spartan 2 & 3 devices still in production for the time being, they're expensive starting at $8-10 with 400-1.5k logic elements on digikey.
The smallest Xilinx devices recommended for new designs looks to be the Spartan-6 series XC6SLX4. They offer ~4k LE (logic elements) and start around $10 with online pricing. This is beyond the scale of most NES mapper interest, perhaps it's not a bad option if you're looking for MMC5 scale capability and beyond.
Xilinx simply doesn't offer much in our target market of 32-1k macrocell/LE anymore, for this reason they're mostly dead to me..
Altera Quartus II & Prime: Which one you use depends on your family of CPLD. The max 10 uses Prime, and I believe max 5 uses QII. I have limited experience with these, what few projects I've used them for I've had no complaints. The software was stable and seemed on par with Xilinx ISE. From what I hear from peers and my limited experience I would recommend Altera for someone who's learning logic design.
At the end of 2016, Altera announced EOL of their only remaining 5v tolerant family EPM3000. So they're very much in the same boat with XC9500XL series. But there's hope for Altera's 3v only devices.
Altera MAX V:
Their smallest current series is max 5 which is 3v only and comes in 32-1.7k 'equivalent macrocells'. They're a bit annoying for two reasons though. They all require 1.8v core supply, so you'll likely need both a 1.8v and 3.3v regulator on board. The smallest device 5M40 only comes in MBGA & EQFP (with 0.4mm pitch) packages. 0.4mm EQFP is better than it only being offered in MBGA, but that extra fine pitch on EQFP-64 packages. These facts paired with requirement for level shifters kinda makes the 5M40 unreasonable for multi-chip discrete to MMC1 scale mappers.
The 5M80/160/240/570 are offered in 0.5mm EQFP-100 packages though. The 5M80 should fit a full fledged MMC1 with room to spare for extras and costs under $2 online. The 5M160 wouldn't fit a full MMC3, but would fit a simplified version with CHR registers trimmed to 32KB CHR-RAM. The 5M240 would be required for full fledged MMC3. Online pricing for the 5M160/240 is $3-5, but I can say volume quoted pricing is pretty competitive to Lattice's offerings in this range.
Altera MAX 10:
From what I understand these are Cyclone FPGAs with flash that configures the logic at power up effectively making it comparable to a CPLD. They start at 2k logic elements and are offered in 0.5mm EQFP-144 and BGA packages. They're comparable to Xilinx's spartan6 series from what I can tell in logic density and online pricing. Unless you can get preferred pricing with a sizable EAU this device is probably out of reach though. It does have the benefit of only requiring a 3.3v supply though.
This is the only software option for LC4000 series devices. I've been using the software routinely since 2015 when I migrated from Xilinx xc9500xl devices. From my experience it's terribly unstable, I've used it quite a bit and it crashes frequently. I think it's also safe to say that it's effectively no longer being maintained by lattice. If you find an issue it's unlikely it'll ever get repaired, your only option is to work around it.
Typically when it crashes you only need to restart the program, but this still happens frequently enough to where I find it unacceptable. There are some gotchas to watch out for as well. If you want to have the software create svf files you must select that option buried in the alternative installation options. If you forget to do that, you have to uninstall and reinstall all over again. Additionally it simply cannot handle spaces in your installation nor project path. Make sure you also don't save the project in something like a Dropbox folder. I forget if it just crashes, or won't allow your project to be saved. The error isn't meaningful for project path problems and can be very frustrating when getting started if you don't know to watch out for this.
For me, the inability to use cloud saves is terribly inconvenient when all other software supports them. Sure there are other backup options and I now use them, but they're inconvenient at best.
On windows you have to be very careful with your PC's environment variables especially when installing other make paths. A number of times I've broken leverclassic when setting up some other dev tools, or vice versa. I've never had any issues like this with other programmable logic design software.
The pinout assignment interface is terribly tedious and annoying to work with especially if you need to frequently make changes. I much prefer to have pinout options completed via text file and while I think it may be possible I still haven't managed to make it work so I know resort to the tedious GUI every time.
In the worst case I've had projects that no matter what I do they get in a state where it crashes during synthesis EVERY time. The only solution in this case is for me to create a new project, copy over my source files, redo all the pinout assignments in it's exceedingly tedious interface, and start over. No clue what goes wrong and you can't get an error report from software that crashed to try and find out what you may have done wrong.
Synthesis errors often offer little to no help. When I get in this situation I typically restart the program hoping it doesn't happen again. Or I have to create a fresh project, import source, redo all pin assignments, and now it just compiles no problem.
It's gotten to the point where I'm nearly ready to give up on the LC4032V despite it being the only 5v tolerant 32 macrocell device on the market. At times I've contemplated reverse engineering the configuration bit stream so I can manually design the device configuration. I'm guessing I could get the device to fit more than the software is capable of fitting and it would let me do away with the software's annoyances once and for all.
I've tinkered with the synthesis goals with varying results. Sometimes using 'Lattice LSE' delivers better results than 'synplify' in terms of resource utilization, sometimes 'synplify' is better. Sometimes one crashes and the other doesn't. Having problems and not getting meaningful error messages? Swap to the other synthesis tool and maybe they'll go away, or your design will now work or fit in your device.
Anyway lever classic can be made to work and in my experience if you slap it around enough it'll get the job done. It's been a thorn in my side for going on 3 years now though. If you already have experience with programmable logic design software I expect you'll have better experience. If your a newbie though, I would fear you'll give up on programmable logic all together if lever classic is your first experience.
This is Lattice's the actively maintained design software which is used for Mach-XO devices and beyond. It's relatively decent and I have a fair amount of experience with it over the past 8 years. I've found a number of problems with it but when I bring them up to Lattice they're quick to deliver a patch. Once it only took a day or two when I pointed out the software gave no means to reclaiming JTAG pins as user i/o as advertised in Mach-XO2 data sheets.
I have had issues which I can't fully blame lattice for, but more meaningful errors or warnings sure would be nice at times. I've mistakenly assigned two different drivers to the same signal and the software happily went along and synthesized the design without errors.
I've had some other issues as well where only one synthesis tool (synplify/latticeLSE) will create a physically working design in practice. But an update that came a year later corrected that issue to where both synthesis tools work. In the end I'll give the software the benefit of the doubt that my verilog was poorly defined. At the time I just didn't want to take the time to rewrite everything in my frustration. I'm not sure what the issue was exactly at the time, but now that I've looked back at my old code I can see room for improvement.
On the whole I'm happy with Lattice Diamond and would recommend it's use. I've never had stability issues, and Lattice is actively maintaining it.
5v tolerant Lattice devices:
Lattice is the only option for a 32-64 macrocell device that's 5v tolerant with the ispMACH LC4000 series which costs $1-3 each. I've been told by Lattice that there is no currently planned EOL. It's 5v tolerance is it's selling point and why they are expecting to manufacture for quite some time.
A MMC1 with 256KB PRG-ROM and 128KB CHR-ROM won't fit in 32 macrocells, but an MMC1 with CHR-RAM will. IMO the LC4032V is the next logical step up from a few discrete logic gates. There are 128-512 macrocell options available which could handle an MMC3/FME7 scale mapper, but their cost no longer makes sense if you can handle migrating to a 3v only device.
In general the LC4000 devices are great because of their 5v tolerance, and in practice I've had no issues with the devices. They're also very quick to program (only a few seconds) in comparison to the xc9500xl series which was exceedingly slow and can take a couple mins to program. Their biggest problem is the lever classic design software as you can't use Lattice diamond for the LC4000 series. If you have success with lever classic that's great, I'm envious, perhaps I'm doing something wrong... Personally I like the LC4032V just enough to put up with lever's software headaches. But it's also the ONLY option for 5v tolerance and 32macrocells with 32 gpio. I would have loved to use the xc9500xl for many more years as I prefer it greatly over the LC4000V, but Xilinx had different plans..
3v only Lattice devices:
The Mach-XO 256 is the lowest cost device offering here and costs about $2. But it comes with the added cost of level translation which varies depending on how many signals you have to shift. If you can handle the 0.5mm fine pitch TQFP-100 package and level shifting it can actually be more cost effective than the 5v tolerant LC4064V. So in general this is my go to device when more than 32 macrocells is needed. It's actually a FPGA LUT/FF architecture and has roughly equivalent to 256 macrocells. It also has some nifty features not found in CPLDs such as a 18-26Mhz on chip oscillator. That becomes of use for things like getting around the M2-/ROMSEL delay. The 'free' oscillator also allows you to start designing mappers with fully synchronous logic which can avoid many of the pitfalls of asynchronous mapper design which can be problematic if not designed around the intricacies of FPGA architectures.
A full fledged MMC3 uses about 45% of available resources, and FME7 uses about 55%. So it's quite capable and I've yet to implement a mapper which comes close to fully utilizing the device but have plans to do so in the near future.
If you're looking for more than ~256 macrocells there are a number of options offered by Lattice. The best device depends on your i/o, logic density, and cost requirements. There are a number of cost effective offerings in the Mach-XO2, and iCE40 devices if you're looking to avoid BGA devices.
Cypress has some PSoC offerings with a programmable logic block attached to an ARM mcu. Last time I researched them the amount of logic provided was rather minimal and the cost was rather high if you gain no value from the mcu. Microchip appears to also be offering small amounts of programmable logic attached to AVR cores. It's nice to see programmable logic becoming available in mcus, we can only hope this continues to grow in the future. As it is today, these aren't viable general use programmable logic solutions like the CPLD/FPGAs mentioned above.
Silego's greenpak devices are rather interesting. They only cost $0.20-0.50 but require volumes of 1-3k effectively. They can be powered from 5v, or 3v while being 5v tolerant. They currently have at most 18io, and 17 flipflops. But they also come with on chip oscillators, delay units, comparators, and state machines, aswell as LDOs in the near future. Unfortunately they currently only come in very small QFN packages, but there is a tssop20 package being released this summer. These are great for replacing a small handful of discrete logic ICs provided you can fit within the limited i/o count. They aren't capable of replicating a MMC1, but a custom mapper could be created with a relatively comparable feature set to MMC1.