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PostPosted: Tue Apr 10, 2018 3:48 pm 
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Joined: Wed Mar 09, 2005 9:08 am
Posts: 410
A question to those more skilled in FPGA design that myself...

In my Everdrive experiments, I had an idea to use the built-in PLLs to scale-and-divide the M2 signal to something that would align more closely to the PPU clock. To my disappointment though, the PLL only supports minimum clock rates of 10MHz (IIRC), and the software's wizard wouldn't even allow me to try out a lower clock rate. The Powerpak has a similar limitation judging by the data sheet.

So is the PLL/DLL approach definitely a no-go on the Everdrive? Seems a bit of a shame, given how useful it could be for clocked circuitry.

And has anyone tried using the DLL on the NES CLK signal using the Powerpak? The Powerpak does route the undivided 21..MHz CLK for the frontloader NES to one of the FPGA clock pins, which could be used for prototyping at least... even if you'd have to add your own oscillator to the design to support toploaders and Famicoms. But ideally being able to synthesize a higher clock from the M2 would be preferable.


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