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PostPosted: Thu Apr 26, 2018 12:57 pm 
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Joined: Tue Feb 27, 2018 10:41 am
Posts: 58
Location: Brazil
infiniteneslives wrote:
Primarily because of it's complexity. It requires a large amount of expensive hardware, and it's functionality is still not 100% known.

infiniteneslives wrote:
Like it or not, but it's the repro market that has helped create the options that homebrewers now have available to them.

It's clear now. Thanks!

infiniteneslives wrote:
All that said if you have a homebrew game that utilizes MMC5 features and can communicate the specifics it makes creation of a potentially simplified board specific for your needs. It's much easier to recreate MMC5 only for your specific needs that are well known, than a 100% accurate MMC5 replica for that's not known as well.

My current boards used for MMC3/FME7 only use about half the available logic resources. They can fully decode the CPU bus, but only enough of the PPU bus to implement MMC2/4. If you can come up with a subset of MMC5 that fits in the current board design you can effectively get it for roughly the same cost as MMC3.

Good to know that the possibility to build such board exists

_________________ | github

PostPosted: Thu Apr 26, 2018 3:10 pm 

Joined: Sun Jun 12, 2011 12:06 pm
Posts: 574
Location: Poland
Of course I did a few MMC5 boards that support subset of MMC5 features, used by some remakes (Super Mario All Stars, Zelda Legend of Link). By just implementing the needed features, I was able to fit even in EPM240 CPLD:
* Different PRG/CHR bankins schemes,
* Scanline couter (the way MMC5 it does by waiting for three consecutive PPU read fetches - but I just limited it to observing A13),
* different bank for sprites & background (SM All Stars used it),
* EXRAM used as additional CPU-RAM (used by utilizing external 64 kB RAM).

The board that I used has wired to CPLD: !ROMSEL, CPU-R/!W, M2, CPU A0-A14, D0-D7, PPU !WE, PPU-A10-A13.
I just had to add PPU !RD signal.

Things that are harded to implement is EXRAM used by both CPU & PPU. It requires CPLD that has resources for implementing internal 1024 bits of dual port RAM, most larger FPGA (Spartan XC3S100E) can do it but they need external configuration meomry and so the initialization takes tens of ms and the CPU need to be haltet for that time. But maybe using external memory + 74245 would be the choice (like pirated MMC5 bootlegs do)

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