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PostPosted: Sat Jul 07, 2018 2:42 pm 
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If an integrated circuit goes inside a NES or Famicom, the failure of the part may not require the scrapping of the whole system. An exact substitute may not be on hand, so here is a list I have cobbled together of drop in replacement parts :

Official Nintendo Systems :

40H368 - 74HC368
74LS139 - 74HC139
74LS373 - 74HC373
RP2A03 - RP2A03E, G, H (unless you don't want the short noise functionality)
RP2C02B - RP2C02C, D, E, G, H (also RP2C03 RGB PPUs with mods, the RP2C05 with $2000/2001 flipping circuitry but I wouldn't trust the RP2C02A)
SRAM - Any 16Kbit/2KB, 8-bit +5v chip, 200ns or lower that will fit. Some cartridges use 8KB/64Kbit or 32KB/256Kbit 8-bit chips.
74HCU04 - 74HC04?, 74HCT04?
BU3266 - BU3270?
3193 - 3193A, 6113, 6113A, 6113B1

Famicom Disk System :

RP2C33 01 - RP2C33A-01A, RP2C33A 02 (note the logo change on the boot screen for the 02 from the Twin Famicom)
LH2838 - 4 x 16Kbit x 4 DRAMs, 150ns or better

Cartridges :

MMC1 - MMC1 & MMC1A must be used in The Money Game and Tatakae!! Ramen Man: Sakuretsu Choujin 102 Gei, otherwise those and MMC1B1, MMC1B2, MMC1B3, and MMC1C can be used in any other game.

MMC3 - MMC3A and non-Sharp MMC3Bs should not be used on games that rely on late MMC3 behavior, (Star Trek 25th Anniversary is the only known licensed game to rely on late MMC3 behavior), otherwise use these or Sharp MMC3Bs or MMC3Cs.

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PostPosted: Sat Jul 07, 2018 2:45 pm 
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LS->HCT, not HC


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PostPosted: Sat Jul 07, 2018 3:50 pm 
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krzysiobal wrote:
LS->HCT, not HC


I have seen boards use the 139 and 373 LS and HC parts interchangeably, but only on pre-GPM Famicoms. NESs and GPM and newer Famicom boards seem to stick with the LS parts for these chips.

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PostPosted: Sat Jul 07, 2018 7:46 pm 
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Also note that the FDS RAM adaptor comes in a few varieties, some containing Fairchild and Sharp SRAMs.

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PostPosted: Sun Jul 08, 2018 6:07 am 
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A 611x lock CIC in the console reportedly won't work with a 319x key in the cartridge. Both 319x works, as does a 611x key with either lock revision.


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PostPosted: Sun Jul 08, 2018 10:20 pm 
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ccovell wrote:
Also note that the FDS RAM adaptor comes in a few varieties, some containing Fairchild and Sharp "SRAMs".


The FDS RAM Adapter always used standard 8K SRAM chips for the CHR-RAM, but always used DRAM for the PRG-RAM. The early revisions of the FDS RAM Adapter come with four 16Kx4 DRAM chips, but later revisions come with a single chip that looks like an SRAM chip but functions like a DRAM chip. This "SRAM" chip is not a common part but should be replaceable if you design a board to wire up the four standard DRAM chips appropriately.

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PostPosted: Mon Jul 09, 2018 1:30 am 
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The pinout of the 32KiB DRAM used in certain models is its own unique thing.

But one should be able to do a small amount of rework to replace it with a conventional 32KiB SRAM. Many of the needed signals—CPUD[0..7], CPUA[7,13,14], R/W, M2, /ROMSEL—are already available from its footprint. The only question in my mind is whether one could use /CAS0, /CAS1, or /RAS, or whether one would have to manually decode the $6000-$DFFF region again.


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PostPosted: Mon Jul 09, 2018 10:15 am 
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lidnariq wrote:
The pinout of the 32KiB DRAM used in certain models is its own unique thing.

But one should be able to do a small amount of rework to replace it with a conventional 32KiB SRAM. Many of the needed signals—CPUD[0..7], CPUA[7,13,14], R/W, M2, /ROMSEL—are already available from its footprint. The only question in my mind is whether one could use /CAS0, /CAS1, or /RAS, or whether one would have to manually decode the $6000-$DFFF region again.


You could decode the region, but I think the 2C33 already does that for you because those Column and Row Access Strobe signals should not be active unless the CPU is trying to read from or the 2C33 is trying to write to that memory area.

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PostPosted: Mon Jul 09, 2018 10:47 am 
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It's true, /RAS must decode the region, but the timing may not be compatible. And /RAS may be active at other times, too, depending on the kind of refresh.

We don't have really any documentation about the DRAM interface. Nothing I couldn't solve with access to an FDS, an oscilloscope, and an hour, but.


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