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PostPosted: Wed Aug 15, 2018 9:15 am 
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The Bung Game Master copier is special amongst all of the "NES era" copiers in that the games do not need to have their mapper writes modified to work with idiosyncratic copier mapper registers. Instead, the device has a Xilinx XC3042 FPGA that can emulate any NES-era mapper:
Attachment:
GameMaster_PCB.jpg
GameMaster_PCB.jpg [ 69.83 KiB | Viewed 1544 times ]
(Picture and info by Tomy)

The FPGA bitstream data is included on the game disk itself for one-game mappers, while for standard mappers such as the MMC1 or MMC3, loading the game is preceded by loading the bitstream data from the appropriate mapper disk (called "preboot"), as this video demonstrates (preboot disk "M" is the disk for 256KiB PRG/128 KiB CHR MMC3).

A high-level emulation of this copier would be trivial by just reusing the normal MMC1 and MMC3 etc. emulation code. A true hardware-level emulation on the other hand would emulate the FPGA and make use of the bitstream data. I've read that the format of such bitstream data is undocumented, but given the age of that particular FPGA, I could imagine that its format has since been released or reverse-engineered, and emulators might even be available. I didn't find any, but maybe I didn't look in the right places?


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PostPosted: Wed Aug 15, 2018 10:14 am 
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Location: NE Indiana, USA (NTSC)
So it's a PowerPak that uses floppies instead of CompactFlash.

What's that 50-pin CON3 at the left? SCSI? If it can be adapted to ATA, then you could probably plug a CF card into it, and it'd be literally a PowerPak.


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PostPosted: Wed Aug 15, 2018 12:01 pm 
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The XC3000 datasheet doesn't give enough information to emulate it, but does give enough information to scope the problem:

The XC3042 has 144 "Configurable Logic Blocks" (what more modern FPGAs seem to call "LUT5s" plus two muxes and two latches) and 96 "Input/Output Blocks". The former should require somewhere around 5+8 bits of configuration per; the latter should require somewhere around 10.

We are told that the total fusemap is 30784 bits; I've only accounted for 2832 above. I suppose it's possible that the remaining 28k bits are all for fabric—if you look at the datasheet they provided a visual tool ("Design Editor" ?) to route signals between macrocells. Assuming its map-like output is a reasonable proxy for reality, the vast majority of bits in the fusemap (maybe not 90% but easily 75%) are fabric.

I imagine emulation of the fabric would tank performance of an emulation.

It's an old and simple enough product you might actually get a result from asking Xilinx for information about the bitstream.


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PostPosted: Wed Aug 15, 2018 12:08 pm 
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lidnariq wrote:
30784 bits
That makes sense, because the bitstream data is always 4096 bytes*8 =32768 bits large. For what it's worth, attached find the bitstream data for a simple mapper, Mapper 148.


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PostPosted: Wed Aug 15, 2018 12:23 pm 
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The datasheet says that the standard encapsulation starts with a 40-bit header. If you skip that, the next 216x142 bits make a ... uh ... identifiable 1bpp bitmap?

Far too many bits are set to be able to guess what's fabric and what's macrocell, though.


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