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PostPosted: Tue Sep 18, 2018 1:38 pm 
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動動腦 II: 國中英文(一), also known as Middle School English II, is commonly available as a Mapper 3 hack. The original Sachen 3014 board is somewhat more involved: The 8 KiB CHR-ROM bank is (apparently) selected by D4 rather than D0 of the CHR-ROM latch. That is nothing special, but the game repeatedly reads $E000 and expects D0-3 to resemble what was previously written to the latch in D4-7, most likely as a simple protection measure. Oddly enough, the game reads $E000 ten times if the value doesn't match what it expects before giving up and resetting.

I want to assign NES 2.0 Mapper 533 for this, but wanted to ask whether based on these images, there is something else to consider other than what I described.

Cartridge and pictures by MLX.
Attachment:
SA003-front.JPG
SA003-front.JPG [ 1.43 MiB | Viewed 3305 times ]

Attachment:
SA003-back.JPG
SA003-back.JPG [ 1.32 MiB | Viewed 3305 times ]


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PostPosted: Tue Sep 18, 2018 2:51 pm 
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The 74193 and 74LS367 both do the obvious thing: latch the upper nybble of the data bus, and drive the latched bits onto the lower nybble of the data bus. But I can't see enough of the traces on the 74LS138 and 74LS02 to make sure I'm understanding correctly.

I'm not even certain if anything keeps the ROM from getting in a fight with the 74LS367, which if true might explain the "rereads ten times" behavior.


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PostPosted: Wed Sep 19, 2018 10:07 am 
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Some of those traces are very confusing.

74'02
Code:
01 - 05 - 06
02 - 138.06 - pin14
03 - 138.04 - 138.05 - pin44
04 -193.11
05 - see 01
06 - see 01
07 - GND
08~13 - NC
14 - 5V


74'138
Code:
01 - pin33
02 - pin34
03 - pin35 (+?)
04 - 05 - 02.03
05 - see 04
06 - 02.02 - (…)
07 - NC
08 - GND
09 - 367. 01 - 367.15
10~15 - NC
16 - 5V


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PostPosted: Wed Sep 19, 2018 10:28 am 
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Location: Seattle
74'02
Code:
01 - 05 - 06
02 - R/W
03 - /ROMSEL
04 - 74193./Latch
05 - see 01
06 - see 01
07 - GND
08~13 - NC
14 - 5V
The 74'02 and 74'193 just latch the contents of the data bus on writes to $8000-$FFFF.

74'138
Code:
01 - CPUA12
02 - CPUA13
03 - CPUA14
04 - /ROMSEL
05 - /ROMSEL
06 - R/W
07 - NC
08 - GND
09 - 74367./OE
10~15 - NC
16 - 5V
Ok, the 74'138 and 74'367 together do nothing but drive its output on reads from $E000-$EFFF.

So... yes, there's nothing to prevent bus conflicts, and I guess the code assumes that the ROM's output drivers will get warm and less capable of emitting current after fighting with the 74'367 repeatedly.


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PostPosted: Wed Sep 19, 2018 10:34 am 
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Does this mean that when reading $E000-$EFFF to get the latch contents into D0-D3, D4-D7 will still reflect the ROM content rather than open bus?


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PostPosted: Wed Sep 19, 2018 10:44 am 
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Oh, actually, there's one more trace that I couldn't figure out from the photos: what is PRG ROM pin 20 connected to?


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PostPosted: Wed Sep 19, 2018 11:27 am 
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It is grounded.


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PostPosted: Wed Sep 19, 2018 11:44 am 
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Ok!

In that case: yes, D4-D7 will still reflect the ROM content rather than open bus.

(In fact, D0-D3 will also, although dumping their contents will be harder given the bus conflicts)


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