No new findings but maybe some ideas. I took MMC5.97 (CL3), through a 500 ohm resistor, to each of the unknown pins (including SL3), then ran my test again, this time looking to see if the MMC5 drove the CPU data bus when reading from $5800. I also tried my random test with reads and writes outside of the range $5800-5BFF to see if any random register writes could affect the range of CL3/SL3. The range held true. This is a 1 kbyte range.
It is very strange to use CL3/SL3 to control RAM at $5800-5BFF, as $6000-6FFF already can only be used for RAM. If you were going to put 1k RAM at $5800, why on earth not just put it at $6000 and skip all this weird register business? That doesn't add up. Dual port RAM makes lots of sense, especially how the range $5800-5BFF is exactly the size of 1 nametable, but we seem to be missing some very elusive /CS /WE signals.
Riddle me this:
Code: Select all
CPU Side PPU Side
CPU A0 A0 A0 PPU A0
CPU A1 A1 A1 PPU A1
CPU A2 A2 A2 PPU A2
CPU A3 A3 A3 PPU A3
CPU A4 A4 A4 PPU A4
CPU A5 A5 A5 PPU A5
CPU A6 A6 A6 PPU A6
CPU A7 A7 A7 PPU A7
CPU A8 A8 A8 PPU A8
CPU A9 A9 A9 PPU A9
CPU A10 A10 A10 CHR A10
CPU D0 D0 D0 PPU D0
CPU D1 D1 D1 PPU D1
CPU D2 D2 D2 PPU D2
CPU D3 D3 D3 PPU D3
CPU D4 D4 D4 PPU D4
CPU D5 D5 D5 PPU D5
CPU D6 D6 D6 PPU D6
CPU D7 D7 D7 PPU D7
GND /OE /OE PPU /A13
CL3 /CE /CE PPU /RD
SL3 /WE /WE PPU /WR
RAM +CE +CE +CE VCC
In this situation, we have 1 nametable mapped to CPU address range $5800-5BFF. Basically creating a different extended RAM for the other side of the vertical split screen. $5800-5BFF on one side of the split, $5C00-5FFF on the other side of the split. I guess that would play into the whole "ease of programming" thing because you could write to both sides the same way. But honestly it isn't really any different than writing to the PPU the normal way, maybe worse because now you don't have auto-increment PPU address, so I am not really sure where I am going with that idea.
Edit:
I realized on the way home that the PPU /A13 won't work, it will always enable the RAM, out of control of the MMC5... So that can't actually work that way.