2A03 external bus signals on internal register accesses

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jaholmes
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2A03 external bus signals on internal register accesses

Post by jaholmes » Sun Jun 09, 2019 8:29 pm

(First post! Woo-hooo!!)

I have a question about the 2A03's bus signals: Do these always behave the same way for internal register accesses as they do for external accesses? For e.g.: Does writing something to $4000 cause that something to appear on D[7:0], $4000 to appear on A[15:0], R/W to go low? Brad Taylor's vintage 2A03 Technical Reference states, "Reads from $4016 and $4017 are decoded inside the 2A03, and those signals are available externally." I'm guessing the whole truth is simpler and more general than this, but it doesn't appear to be discussed at all in the more-recent Wiki treatment. (Although I've been known to miss things. Often.)

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Memblers
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Re: 2A03 external bus signals on internal register accesses

Post by Memblers » Sun Jun 09, 2019 8:58 pm

Welcome. I think everything shows up on the CPU bus. My understanding is that the only thing hidden from cartridges are accesses to the PPU at $3F00-$3FFF.

jaholmes
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Re: 2A03 external bus signals on internal register accesses

Post by jaholmes » Sun Jun 09, 2019 9:50 pm

Memblers wrote:Welcome. I think everything shows up on the CPU bus. My understanding is that the only thing hidden from cartridges are accesses to the PPU at $3F00-$3FFF.
Ok, that's very good to know. *Crosses a few doomed ideas off the list!* For context, I'm actually working on vNext of this thing. To the implied question of why I didn't stick a logic analyzer on it and try to answer my own question: It's currently with a friend who wanted to MIDI-ize it, leaving me with only thought experiments to conduct. Shamefully, I don't own any other 2A03-based devices--no NES! (But I have a decent Virtual Console library! :))

The device in the video has a stupidly simple external memory map, with RAM at $C000+ and nothing else. There isn't even a stack. But, after fighting with myself for a few weeks, I've decided that vNext should be capable of playing even the most egregious Famitracker-made abuses of the delta modulation channel, meaning that I finally have to get into bankswitching and all that. So! Trying to fill out my understanding of the bus behaviors so I can hold to the KISS principles of the existing design while still getting to where I want to go. It won't be an NSF player, but it will be something slightly more than a VGM player.

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Re: 2A03 external bus signals on internal register accesses

Post by lidnariq » Sat Jun 22, 2019 12:10 pm

jaholmes wrote:I have a question about the 2A03's bus signals: Do these always behave the same way for internal register accesses as they do for external accesses?
The only thing that does not show up externally with the 2A03 is reads from $4015, which happens from a special 2A03-internal bus.

For the 2C02, what Memblers said.

jaholmes
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Re: 2A03 external bus signals on internal register accesses

Post by jaholmes » Sat Jun 29, 2019 12:59 pm

lidnariq wrote:
jaholmes wrote:I have a question about the 2A03's bus signals: Do these always behave the same way for internal register accesses as they do for external accesses?
The only thing that does not show up externally with the 2A03 is reads from $4015, which happens from a special 2A03-internal bus.

For the 2C02, what Memblers said.
Thanks lidnariq! I suppose that if the 2A03 is in test mode, reads from the test registers will appear on the external data bus. That might be an interesting way to quickly replicate the DAC values into some external device--e.g. for display. Right now, I'm using partial emulation to generate the LED states, which seems dumb in hindsight. (I hadn't read about test mode until I'd built all of that.)

Anyway, I decided it would be amusing to use an old 22V10 PAL (actually GAL) for bus cycle / address deciding in v.Next, which makes my original reason for posting kinda moot. (I had been cooking up various ultra-minimalist memory mapping schemes in my head.)

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Re: 2A03 external bus signals on internal register accesses

Post by lidnariq » Sat Jun 29, 2019 1:11 pm

jaholmes wrote:Thanks lidnariq! I suppose that if the 2A03 is in test mode, reads from the test registers will appear on the external data bus.
No. I didn't mention that because I didn't think it was relevant. In test mode, reads from the entire region $4000-$401F are from the special internal bus, instead of only reads from $4015.

jaholmes
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Re: 2A03 external bus signals on internal register accesses

Post by jaholmes » Sat Jun 29, 2019 1:15 pm

lidnariq wrote:No. I didn't mention that because I didn't think it was relevant. In test mode, reads from the entire region $4000-$401F are from the special internal bus, instead of only reads from $4015.
Oh, snap. Well, I've got a DP ram between the 2A03 and the MCU, so with a few more cycles, I can fetch things that way.

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Re: 2A03 external bus signals on internal register accesses

Post by supercat » Sat Jun 29, 2019 1:25 pm

lidnariq wrote:
jaholmes wrote:I have a question about the 2A03's bus signals: Do these always behave the same way for internal register accesses as they do for external accesses?
The only thing that does not show up externally with the 2A03 is reads from $4015, which happens from a special 2A03-internal bus.

For the 2C02, what Memblers said.
What happens on the external bus during such reads? I would guess that such reads would appear on the external bus as normal reads, but the CPU wouldn't actually do anything with any value placed on the external bus; is that what happens, or does it suppress the phi2 (M2) cycle, or something else?

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Re: 2A03 external bus signals on internal register accesses

Post by lidnariq » Sat Jun 29, 2019 1:48 pm

To the outside world it looks like a normal read, but the CPU inside never receives the value. (Visual2A03 "dbe" prevents the outside world from being relayed; "dbe" is a function of R/W, /R4015, +TEST, and /R40xx).

I can't think of a way for software to detect that the undriven addresses (i.e. $4000-$4014, $4016, $4017, $401B-$401F) are isolated from the outside world when in test mode. But a dummy read from one of the four driven addresses will show that they don't reach the outside world. (i.e. ldx #$80 / lda $4095,x could acknowledge a frame interrupt but A wouldn't hold the contents of $4015)

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