Recover PPU./WR when ppu writes to palette, possible?

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Haruka
Posts: 45
Joined: Fri Mar 23, 2018 8:58 pm

Recover PPU./WR when ppu writes to palette, possible?

Post by Haruka » Tue May 26, 2020 8:48 pm

I'm not quite clear of the sync between CPU and PPU, and signal timing on the PPU pins.
Let's assume I'm currently writing to the palette through PPU registers $2006 and $2007:

Code: Select all

lda #$30
sta $2006
lda #$00
sta $2006
lda #$3F
sta $2007
when the last code "sta $2007" is executed (or is executing? I'm not sure...) on the CPU, 0 is asserted on PPU./CS indicating the PPU being selected, $7 is asserted on CPU.A0~CPU.A2 indicating the PPU register $2007 being selected, 0 is asserted on CPU.R/W indicating the register $2007 is being written to, value $3f is asserted on the CPU data bus indicating the value being written to reg $2007. Am I correct?
But when does the PPU asserts address, data and control signals on its buses so the data comes into the internal palette RAM? Immediately after the CPU fed it from its CPU-side pins? Or one PPU cycle after the CPU fed it? Or several cycles?
According to thishttp://wiki.nesdev.com/w/index.php/PPU_ ... escription article, PPU./WR is not asserted when PPU is writing to palette. Can we recover this signal from the operation of the CPU side? i.e. when PPU.A0~PPU.A13 == $3F00~$3FFF && PPU./CS == 0 && PPU.CPU A0~PPU.CPU A2 == $07 && PPU.CPU R/W == 0?

Could anyone please give me some hints? or correct me if I'm wrong?

lidnariq
Posts: 9838
Joined: Sun Apr 13, 2008 11:12 am
Location: Seattle

Re: Recover PPU./WR when ppu writes to palette, possible?

Post by lidnariq » Tue May 26, 2020 9:02 pm

Haruka wrote:
Tue May 26, 2020 8:48 pm
when the last code "sta $2007" is executed (or is executing? I'm not sure...) on the CPU, 0 is asserted on PPU./CS indicating the PPU being selected, $7 is asserted on CPU.A0~CPU.A2 indicating the PPU register $2007 being selected, 0 is asserted on CPU.R/W indicating the register $2007 is being written to, value $3f is asserted on the CPU data bus indicating the value being written to reg $2007. Am I correct?
Yes.
But when does the PPU asserts address, data and control signals on its buses so the data comes into the internal palette RAM?
Writes to palette RAM happen on the same FSM as writes to PPU memory; the only difference is that it never actually asserts /WR. (So: a couple pixels later)
Can we recover this signal from the operation of the CPU side? i.e. when PPU.A0~PPU.A13 == $3F00~$3FFF && PPU./CS == 0 && PPU.CPU A0~PPU.CPU A2 == $07 && PPU.CPU R/W == 0?
I mean, sure, but what for? I mean, other than the NESRGB and HDNES kits, which rely on replacing the value that the CPU writes to the PPU.

Haruka
Posts: 45
Joined: Fri Mar 23, 2018 8:58 pm

Re: Recover PPU./WR when ppu writes to palette, possible?

Post by Haruka » Tue May 26, 2020 10:15 pm

lidnariq wrote:
Tue May 26, 2020 9:02 pm
Can we recover this signal from the operation of the CPU side? i.e. when PPU.A0~PPU.A13 == $3F00~$3FFF && PPU./CS == 0 && PPU.CPU A0~PPU.CPU A2 == $07 && PPU.CPU R/W == 0?
I mean, sure, but what for? I mean, other than the NESRGB and HDNES kits, which rely on replacing the value that the CPU writes to the PPU.
Thank you for your reply!

Wait... NESRGB also uses this method? Impressive!
I'm trying to figure out a solotion for a hardware graphics visualizer. Pattern Table and Name Table accesses are simple, while palette and OAM are blocking my path.

Now that since NESRGB is mentioned, could you please explain more?I'm also quite interested in it.
From what I'm learned, when PPU is writing to palette, NESRGB just cheats PPU and backups the data in its palette RAM. So that the real color can be retrived from this index table and a index -> RGB color LUT using EXT0~3. Am I correct?
PPU fetches color indices from palette RAM on each pixel rendering, that is to say, PPU asserts PPU.Ax and PPU./RD, and data appears on PPU.Dx. Am I correct? I highly doubt my conclusion. Maybe this is an internal operation so the external pins won't perform any behavior?
At the same time during each pixel rendering, PPU also emits palette indices to EXT0~3, so NESRGB now reads the backup palette RAM (together with color LUT) and then get the final color. Am I correct?

lidnariq
Posts: 9838
Joined: Sun Apr 13, 2008 11:12 am
Location: Seattle

Re: Recover PPU./WR when ppu writes to palette, possible?

Post by lidnariq » Tue May 26, 2020 11:23 pm

Haruka wrote:
Tue May 26, 2020 10:15 pm
From what I'm learned, when PPU is writing to palette, NESRGB just cheats PPU and backups the data in its palette RAM. So that the real color can be retrived from this index table and a index -> RGB color LUT using EXT0~3. Am I correct?
Yes. Specifically, the NESRGB and HDNES keep track of the original written value, and replace the value that would have been written with black and white, to mark sprite vs background pixels.
PPU fetches color indices from palette RAM on each pixel rendering, that is to say, PPU asserts PPU.Ax and PPU./RD, and data appears on PPU.Dx. Am I correct?
No...
I highly doubt my conclusion. Maybe this is an internal operation so the external pins won't perform any behavior?
Yes.
At the same time during each pixel rendering, PPU also emits palette indices to EXT0~3, so NESRGB now reads the backup palette RAM (together with color LUT) and then get the final color. Am I correct?
Almost. The tricky part is that there are 5 bits of color index, but there are only 4 bits of EXT pins, which is why the PPU's video output has to be coerced into serving as a fifth bit.

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