Let's assume I'm currently writing to the palette through PPU registers $2006 and $2007:
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lda #$30 sta $2006 lda #$00 sta $2006 lda #$3F sta $2007
But when does the PPU asserts address, data and control signals on its buses so the data comes into the internal palette RAM? Immediately after the CPU fed it from its CPU-side pins? Or one PPU cycle after the CPU fed it? Or several cycles?
According to thishttp://wiki.nesdev.com/w/index.php/PPU_ ... escription article, PPU./WR is not asserted when PPU is writing to palette. Can we recover this signal from the operation of the CPU side? i.e. when PPU.A0~PPU.A13 == $3F00~$3FFF && PPU./CS == 0 && PPU.CPU A0~PPU.CPU A2 == $07 && PPU.CPU R/W == 0?
Could anyone please give me some hints? or correct me if I'm wrong?