When I was looking into the Channel F schematics, I mentioned a clock multiplier that multiplies the 3.6MHz clock for chroma by 8/7 to generate the pixel clock:
- digital-8-7ths-rate-multiplier.png (2.15 KiB) Viewed 327 times
(This resulting clock isn't uniform, so when divided by 2 again for the pixel clock the pixels shouldn't be uniform width either. Every other column should alternate between 9:14 and 12:14 PAR, averaging out to a PAR of 3:4)
This can easily be generalized to any number of the form 2ⁿ÷(2ⁿ-1) by changing the number of clock dividers, including just 2÷1:
- digital-edge-detector.png (1.52 KiB) Viewed 327 times
Although a simpler design may be preferable for that specific case:
- but R·C << 1/f
- hybrid-edge-detector.png (1.27 KiB) Viewed 327 times
Given other parts or multiple ICs, any ratio of the form 2·n÷(2·n-1) can be made also:
- digital-10-9ths-rate-multiplier.png (2.38 KiB) Viewed 327 times