Final Fantasy V (Yancheng cy2000-3 PCB, mapper 164)

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krzysiobal
Posts: 753
Joined: Sun Jun 12, 2011 12:06 pm
Location: Poland

Final Fantasy V (Yancheng cy2000-3 PCB, mapper 164)

Post by krzysiobal » Mon Sep 07, 2020 3:31 pm

Analysis requested by NewRisingSun. This PCB contains:
* 512kB PRG-ROM
* 2kB PRG-RAM
* 93C46 based EEPROM2 PRG-RAM
* 93C46 based EEPROM1 PRG-RAM (unpopulated)
* 8kB blob CHR-RAM
* mapper blob

Image Image Image Image

ROM: https://gofile.io/d/fKIT60

Code: Select all

             +--------+ 
   CPU D5 -> | 01     |
   CPU D4 -> | 02     |
   CPU D3 -> | 03  46 | -- +5V
   CPU D2 <> | 04  45 | <- CPU D6
   CPU D1 -> | 05  44 | <- CPU D7
   CPU D0 -> | 06  43 | <- PPU A13
        ? -> | 07  42 | <- CPU A9
  PPU /RD -> | 08  41 | <- PPU A10
  PPU A3  -> | 09  30 | <- PPU A11
  PPU A12 -> | 10  39 | -> PRG A19
  CHR A12 <- | 11  38 | -> CIR A10
  CHR A3  <- | 12  37 | -> PRG /OE
  PPU A9  -> | 13  36 | -> PRG A18
  PPU A0  -> | 14  35 | -> PRG A17
  WRAM/CE <- | 15  34 | -> PRG A16
  CPU A10 -> | 16  33 | -> PRG A15
  CPU A11 -> | 17  32 | -> PRG A14
  CPU A12 -> | 18  31 | <- CPU A8
 EPR DOUT -> | 19  30 | <- CPU A14
  CPU A13 -> | 20  29 | <- /RESET
       M2 -> | 21  28 | <- CPU /ROMSEL
  EPR DIN <- | 22  27 | -> $5000.6
  EPR CLK <- | 23  26 | -> EPR1 CS
  EPR2 CS <- | 24  25 | -- GND
             +--------+
			 Mapper blob pinout

* While /RESET=0, all bits of internal registers are being cleared (writes are ignored)
* Mapper chip does use CPU R/W, so it cannot distinguish between CPU reads and writes
(all access to $5000/$5100/$5200/$5300 is treated as writes and all access to $5500 as reads)
* Pin 7 is unknown input (internally pulled-up high). Changing its level does not alter
PRG banking behaviour nor its value can be read back in $5500.

----------------------------- Register $5000 -------------------------
D~7654 3210
  ---------
  CSQM PPPp
  ||+|-++++- PRG bank (see table below)
  |+-+------ PRG banking mode 
  |  +------ value of this bit is also output on pin 27
  |  +------ 1=enables mirroring control by $5300.7, 0=ignores $5300.7 and forces mirroring to V
  +--------- 1 bpp video mode: when PPU A13=0 (pattern table) ...
              0: CHR A3=PPU A3, CHR A12=PPU A12 (disable 1 bpp mode)
              1: CHR A3=PPU A0, CHR A12=PPU A9, both latched on
                 last rise of PPU A13 (enable 1 bpp mode)

S M   QPPPp  | $8000 $C000
-------------+------------
0 0    any   | QPPPp   $1F     
             |
1 0 $00..$1B | QPPPp   $1E
1 0 $1C..$1F | QPPPp   $1C
             |
1 1 $00..$0F | PPPp0 PPPp1
1 1 $10..$17 | 0PPPp   $0F
1 1 $18..$1F | 1PPPp   $1F
             |
0 1    any   |   open bus   (See note 1)

Note 1: For that case, PRG A18..A14 are still driven the same way as when S=1 and M=1,
but PRG/CE is always held at 1, so effectively it is open bus for reads from $8000-$ffff
I have no idea what it can be used for.

----------------------------- Register $5100 -------------------------
D~7654 3210
  ---------
  .... ...X
          +- PRG A19
----------------------------- Register $5200 -------------------------

D~7654 3210
  ---------
  .s.S .C.D
   | |  | +- 93C66 EEPROM DAT output
   | |  +--- 93C66 EEPROM CLK output
   | +------ 93C66 EEPROM2 CS output 
   +-------- 93C66 EEPROM1 CS output (non populated)
   
----------------------------- Register $5300 -------------------------

D~7654 3210
  ---------
  m... ....
  |
  +--------- mirroring: 0=H, 1=V

NewRisingSun
Posts: 1215
Joined: Thu May 19, 2005 11:30 am

Re: Final Fantasy V (Yancheng cy2000-3 PCB, mapper 164)

Post by NewRisingSun » Wed Sep 09, 2020 8:06 am

Thank you, krz. A couple of points:
  • Which bit is output to pin 27? The pin description says $5000.6, but the register $5000 description implies $5000.4.
  • The "open bus" setting comes from the Dongda Pyramid Educational Computer PEC-9588, on which this chipset was originally used, where it selects between several cartridge slots.
  • Your dump is very different to the existing dump, indicating a different revision of the game.

krzysiobal
Posts: 753
Joined: Sun Jun 12, 2011 12:06 pm
Location: Poland

Re: Final Fantasy V (Yancheng cy2000-3 PCB, mapper 164)

Post by krzysiobal » Wed Sep 09, 2020 3:30 pm

$5000.4
Maybe the unknown pin 7 has something to do with the 1bit mode - this is the only part that I did not confirm yet.

calima
Posts: 1186
Joined: Tue Oct 06, 2015 10:16 am

Re: Final Fantasy V (Yancheng cy2000-3 PCB, mapper 164)

Post by calima » Thu Sep 10, 2020 12:57 am

Screenshots? This game doesn't have a page on bootleggames, only a single-line mention.


calima
Posts: 1186
Joined: Tue Oct 06, 2015 10:16 am

Re: Final Fantasy V (Yancheng cy2000-3 PCB, mapper 164)

Post by calima » Thu Sep 10, 2020 9:56 am

:shock:
Even for China stuff, that's some ripping. Title screen from Dark Cloud, world graphics from GBC Zelda, and battle graphics look like that GB pokemon clone where you used a phone to summon monsters.

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