Quick question about /ROMSEL and the '161[SOLVED]

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Fumarumota
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Quick question about /ROMSEL and the '161[SOLVED]

Post by Fumarumota » Wed Sep 09, 2020 11:21 pm

Hi all,

I'm trying to understand how the clock for the CHR (or PRG) bankswitch works for GNROM-like cartridges, the ones that use a '161 as a register.

If I understand well, the clock on the '161 ticks on transitions from low to high. /ROMSEL is low whenever the CPU is accessing $8000-$FFFF, so how can the '161 clock be triggered and latch the inputs with such a signal if it also requires the CPU R/W signal to be low at the same time in order to enable the /LOAD in the '161)?

How the rising edge needed for the clock is generated?

Thank you in advance, and sorry for my English.
Last edited by Fumarumota on Thu Sep 10, 2020 11:36 am, edited 3 times in total.
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lidnariq
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Re: Quick question about /ROMSEL and the '161

Post by lidnariq » Wed Sep 09, 2020 11:35 pm

The 6502 guarantees/requires that:
The R/W line and address bus are correct when φ2 rises
The data bus is correct when φ2 falls.

The CPU does not immediately replace R/W and address bus immediately after φ2 falls. There's enough time for external devices—such as the 74'161—to get its values. And there's nothing else to change the contents of the data bus until much much later.

In the NES, M2 isn't exactly the same as φ2 - it rises earlier. However, the address bus is still valid at this earlier time.

A number of devices, including the PPU, erroneously assume that the data bus is valid the entire time M2 is high. Unfortunately, this isn't true.

/ROMSEL is NAND(A15,M2), so its rising edge is a little later than the falling edge of M2. It still works fine.

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Fumarumota
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Re: Quick question about /ROMSEL and the '161

Post by Fumarumota » Thu Sep 10, 2020 9:45 am

lidnariq wrote:
Wed Sep 09, 2020 11:35 pm
The 6502 guarantees/requires that:
The R/W line and address bus are correct when φ2 rises
The data bus is correct when φ2 falls.

The CPU does not immediately replace R/W and address bus immediately after φ2 falls. There's enough time for external devices—such as the 74'161—to get its values. And there's nothing else to change the contents of the data bus until much much later.

In the NES, M2 isn't exactly the same as φ2 - it rises earlier. However, the address bus is still valid at this earlier time.

A number of devices, including the PPU, erroneously assume that the data bus is valid the entire time M2 is high. Unfortunately, this isn't true.

/ROMSEL is NAND(A15,M2), so its rising edge is a little later than the falling edge of M2. It still works fine.
Wow, cool, that certainly was something new to me.

But still there's something I don't grasp (this may be a really silly question).

Lets say I have the following code to select CHR bank $03 in a CNROM board:

LDA $03
STA $8000

So during the opcode and operand fetches I presume /ROMSEL is low (if PRG-ROM is mapped at $8000 as usual), then during the write in STA it is also low. So I don't see when /ROMSEL goes high in order to clock the '161 (pretty sure I'm missing something).

Thanks folks for all your knowledge sharing.
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lidnariq
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Re: Quick question about /ROMSEL and the '161

Post by lidnariq » Thu Sep 10, 2020 10:17 am

Fumarumota wrote:
Thu Sep 10, 2020 9:45 am
So during the opcode and operand fetches I presume /ROMSEL is low (if PRG-ROM is mapped at $8000 as usual), then during the write in STA it is also low. So I don't see when /ROMSEL goes high in order to clock the '161 (pretty sure I'm missing something).
Because /ROMSEL in the NES is not only /A15, but also includes M2. M2 is both low and high during every access cycle. So STA $8000 is four cycles, three of which is uses to read STA abs, 0, and $80, and the 4th it writes to $8000.

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Fumarumota
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Re: Quick question about /ROMSEL and the '161

Post by Fumarumota » Thu Sep 10, 2020 10:36 am

lidnariq wrote:
Thu Sep 10, 2020 10:17 am
Fumarumota wrote:
Thu Sep 10, 2020 9:45 am
So during the opcode and operand fetches I presume /ROMSEL is low (if PRG-ROM is mapped at $8000 as usual), then during the write in STA it is also low. So I don't see when /ROMSEL goes high in order to clock the '161 (pretty sure I'm missing something).
Because /ROMSEL in the NES is not only /A15, but also includes M2. M2 is both low and high during every access cycle. So STA $8000 is four cycles, three of which is uses to read STA abs, 0, and $80, and the 4th it writes to $8000.
OMG, crystal clear now :). Thanks a lot Lidnariq!
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