I was requested to create a JEDEC file to burn into GAL chip to make clone of the subjected chip. I don't have access to the original cartridge's PAL so here are my efforts (if I'm wrong, feel free to correct me)
1. The most basic GAL (or PAL) chips are the "L" ones, whose outputs can be combinatorial or latched (SET/RESET latch, using internal feedback path).
To define an output (Q) as latched one, that is set to 1 when S=0 and set to 0 when R=0, we can just write it like:
2. More advanced ones are the V chips, whose outputs can be combinatorial, latched or registered (clocked latch).
To define an output (Q) as registered one:
Code: Select all
Q := D
Q.C = some_clock_signal
Q.OE = /some_output_enable_signal
The advantage of registered latch is that it uses less resources than latched one, but the disadvantages are:
* each registered output share the same clock and output enable input
* clock input must come from pin 1 (if more advanced logic function is needed, one of output pins need to be used for such equation and then connected externally to in 1)
* otpuput enable must come from pin 11 (if all regsitered outputs need to be always enabled, pin 11 must be connected externally to GND)
3. This PLD chip is not configured in registered mode, because
a) that would force common clock for all output pins, but audio pins ($9800) and PRG-A pins ($9000) use different address and so need different logic formulas for clock inputs
b) pin 11 is not GND
2. So the PAL need to be configured in latched mode. But because pin19 (=PRG_A16) and pin 12 (=AUD3) are latched outputs, it can't be realised in the most popular 16V8 chip (it has 16 inputs, but out of all I/O pins, only 13..18 can be inputs) and so it needs 18V8 chips (18 inputs = all pins can be used as inputs).
But GAL18V8 are much less common.
* I can't find them on aliexpress,
* the good-old program EQN2JED.EXE does not support them,
* MiniPro, the popular USB programmer does not support them either
So if yout want to stick to GAL16V8, you should reorder the output pins (AUD3=pin12 and CLK_OUT=pin17) to get extra one output but still there would be no place for PRG-A16.
The CLK_IN / CLK_OUT external loop is neccessary because there is not enough logic terms for feedback output of all the inputs to be calculated internally (CPU_R_nW, CPU_ROMSEL, CPU_A14, CPU_A13, CPU_A12)
The only working idea is to:
* forget about all the five inputs (CPU_R_nW, CPU_ROMSEL, CPU_A14, CPU_A13, CPU_A12) and route VRC4_900C instead (to pin 1), because VRC4 computes it in exact the same way.
* route CPU_A11 to pin 2
* move PRG_A16 to pin 17
* move AUD3 to pin 16
As a final result, I burned GAL16V8 with the above file:
and then read-it back using my tester:
and et voila - I got a working logic:
Code: Select all
'0' when (!CPU_D2 & CPU_A11 & !nVRC4_900C) else
'1' when (CPU_D2 & CPU_A11 & !nVRC4_900C);
'0' when (!CPU_D1 & CPU_A11 & !nVRC4_900C) else
'1' when (CPU_D1 & CPU_A11 & !nVRC4_900C);
'0' when (!CPU_D0 & CPU_A11 & !nVRC4_900C) else
'1' when (CPU_D0 & CPU_A11 & !nVRC4_900C);
'0' when (!CPU_D3 & CPU_A11 & !nVRC4_900C) else
'1' when (CPU_D3 & CPU_A11 & !nVRC4_900C);
'0' when (!CPU_D3 & !CPU_A11 & !nVRC4_900C) else
'1' when (CPU_D3 & !CPU_A11 & !nVRC4_900C);
'0' when (!CPU_D2 & !CPU_A11 & !nVRC4_900C) else
'1' when (CPU_D2 & !CPU_A11 & !nVRC4_900C);
q5911 wrote: ↑
Fri Mar 19, 2021 9:14 pm
Hello, can you write this PAL program? Why not use the PRG address of vrc4 this card?
Maybe because this game expects 32kB banks (and also expects PRG bank writes at $900C instead of $9000?)