City Figher 4 with ext audio (Mapper 266)

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krzysiobal
Posts: 832
Joined: Sun Jun 12, 2011 12:06 pm
Location: Poland

City Figher 4 with ext audio (Mapper 266)

Post by krzysiobal » Sat Dec 19, 2020 5:41 pm

The whole story started when trying to make repro of City Fighter 4 (mapper 266)
Image Image

Thanks to wiki, I was able to get how the registers works. It does not say however how the DAC is realized so I made a resistor ladder:
Image Image Image

https://www.youtube.com/watch?v=Dcj0r5pjIVc

Then, somebody shown me how the original PCB looks like so I made a schematic:
Image Image Image Image Image

There are some interesting facts:
* PRG ROM D3 and D5 are reversed (copy protection?)
* The resistor ladder is different than mine.
* Wiki says about using pin /WR900C of VRC4 to decode $900C/$980C, which sounds logical, because together with VRC4's OR gate and CPU-A11 it would work indeed:

Code: Select all

CPU-A11 - |VRC4 OR A     VRC4 OR Y | - WR9800C
       +- |VRC4 OR B               |
       |  |                        |
       |  |                 /WR900C| -+
       |                              |
       +------------------------------+
but instead, PAL is used to perform the decoding and latch six bits (four for AUDIO DAC and two for PRG data)
* Despite using 32kB PRG banks (which would suggest that VRC4 is not involved in PRG banking at all), VRC4 drives PRG-A13 and PRG-A14. To make 32KB banks works as expected:

Code: Select all

$8000 $a000 $c000 $e000
  0      1    2     3 
game should initialize:
* PRG REG0 at $8000 to 0
* PRG REG1 at $a000 to 1 (which is accessed at $c000 because of mixed CPU-A13 and CPU-A14)
and it does it!

Code: Select all

 01:FE96: A9 00     LDA #$00
 01:FE98: 8D 98 93  STA $9398 
 01:FE9B: 8D A0 86  STA $86A0 !
...
 01:FE9E: A9 01     LDA #$01
 01:FEA0: 8D 30 CD  STA $CD30 !
NewRisingSun - you made the wiki description of Mapper 266. Do you have different revision of this cartridge?

NewRisingSun
Posts: 1292
Joined: Thu May 19, 2005 11:30 am

Re: City Figher 4 with ext audio (Mapper 266)

Post by NewRisingSun » Sat Dec 19, 2020 5:51 pm

No, I only debugged the game's code and tried to draw plausible conclusions. 8-)

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Ben Boldt
Posts: 777
Joined: Tue Mar 22, 2016 8:27 pm
Location: Minnesota, USA

Re: City Figher 4 with ext audio (Mapper 266)

Post by Ben Boldt » Sat Dec 19, 2020 6:05 pm

Why do you suppose they added a 4-bit DAC instead of just using the built-in DPCM in the Famicom? Are they already using the DPCM at the same time for a different purpose?

NewRisingSun
Posts: 1292
Joined: Thu May 19, 2005 11:30 am

Re: City Figher 4 with ext audio (Mapper 266)

Post by NewRisingSun » Sat Dec 19, 2020 6:09 pm

I speculated on the wiki that doing so would allow them to add a low-pass filter to make the grungy PCM sound less objectionable.

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aquasnake
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Re: City Figher 4 with ext audio (Mapper 266)

Post by aquasnake » Sun Dec 20, 2020 6:54 am

Your resistor ladder of DAC is better than the original circuit. The output level of the original circuit is not strictly an 8421 code function.(I'm not sure. Maybe the original design made some sense)

q5911
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Joined: Sun Mar 07, 2021 10:36 pm

Re: City Figher 4 with ext audio (Mapper 266)

Post by q5911 » Fri Mar 19, 2021 9:14 pm

Hello, can you write this PAL program? Why not use the PRG address of vrc4 this card?

krzysiobal
Posts: 832
Joined: Sun Jun 12, 2011 12:06 pm
Location: Poland

Re: City Figher 4 with ext audio (Mapper 266)

Post by krzysiobal » Thu Apr 08, 2021 11:45 am

I was requested to create a JEDEC file to burn into GAL chip to make clone of the subjected chip. I don't have access to the original cartridge's PAL so here are my efforts (if I'm wrong, feel free to correct me)

1. The most basic GAL (or PAL) chips are the "L" ones, whose outputs can be combinatorial or latched (SET/RESET latch, using internal feedback path).
To define an output (Q) as latched one, that is set to 1 when S=0 and set to 0 when R=0, we can just write it like:

Code: Select all

Q = /nS + nR * Q

2. More advanced ones are the V chips, whose outputs can be combinatorial, latched or registered (clocked latch).
To define an output (Q) as registered one:

Code: Select all

Q := D
Q.C = some_clock_signal
Q.OE = /some_output_enable_signal
The advantage of registered latch is that it uses less resources than latched one, but the disadvantages are:
* each registered output share the same clock and output enable input
* clock input must come from pin 1 (if more advanced logic function is needed, one of output pins need to be used for such equation and then connected externally to in 1)
* otpuput enable must come from pin 11 (if all regsitered outputs need to be always enabled, pin 11 must be connected externally to GND)

3. This PLD chip is not configured in registered mode, because
a) that would force common clock for all output pins, but audio pins ($9800) and PRG-A pins ($9000) use different address and so need different logic formulas for clock inputs
b) pin 11 is not GND

2. So the PAL need to be configured in latched mode. But because pin19 (=PRG_A16) and pin 12 (=AUD3) are latched outputs, it can't be realised in the most popular 16V8 chip (it has 16 inputs, but out of all I/O pins, only 13..18 can be inputs) and so it needs 18V8 chips (18 inputs = all pins can be used as inputs).

But GAL18V8 are much less common.
* I can't find them on aliexpress,
* the good-old program EQN2JED.EXE does not support them,
* MiniPro, the popular USB programmer does not support them either


So if yout want to stick to GAL16V8, you should reorder the output pins (AUD3=pin12 and CLK_OUT=pin17) to get extra one output but still there would be no place for PRG-A16.
Image

The CLK_IN / CLK_OUT external loop is neccessary because there is not enough logic terms for feedback output of all the inputs to be calculated internally (CPU_R_nW, CPU_ROMSEL, CPU_A14, CPU_A13, CPU_A12)
Image

The only working idea is to:
* forget about all the five inputs (CPU_R_nW, CPU_ROMSEL, CPU_A14, CPU_A13, CPU_A12) and route VRC4_900C instead (to pin 1), because VRC4 computes it in exact the same way.
* route CPU_A11 to pin 2
* move PRG_A16 to pin 17
* move AUD3 to pin 16

As a final result, I burned GAL16V8 with the above file:
Image Image

and then read-it back using my tester:
Image Image

and et voila - I got a working logic:

Code: Select all

AUD2 <= 
 '0' when (!CPU_D2 & CPU_A11 & !nVRC4_900C) else
 '1' when (CPU_D2 & CPU_A11 & !nVRC4_900C);
 
AUD1 <= 
 '0' when (!CPU_D1 & CPU_A11 & !nVRC4_900C) else
 '1' when (CPU_D1 & CPU_A11 & !nVRC4_900C);
 
AUD0 <= 
 '0' when (!CPU_D0 & CPU_A11 & !nVRC4_900C) else
 '1' when (CPU_D0 & CPU_A11 & !nVRC4_900C);
 
AUD3 <= 
 '0' when (!CPU_D3 & CPU_A11 & !nVRC4_900C) else
 '1' when (CPU_D3 & CPU_A11 & !nVRC4_900C);
 
PRG_A16 <= 
 '0' when (!CPU_D3 & !CPU_A11 & !nVRC4_900C) else
 '1' when (CPU_D3 & !CPU_A11 & !nVRC4_900C);
 
PRG_A15 <= 
 '0' when (!CPU_D2 & !CPU_A11 & !nVRC4_900C) else
 '1' when (CPU_D2 & !CPU_A11 & !nVRC4_900C);
q5911 wrote:
Fri Mar 19, 2021 9:14 pm
Hello, can you write this PAL program? Why not use the PRG address of vrc4 this card?
Maybe because this game expects 32kB banks (and also expects PRG bank writes at $900C instead of $9000?)
Attachments
proj_eqn+jed+log.zip
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