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PostPosted: Sun Oct 29, 2006 11:02 am 
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Well, I don't think so. All I can say is that at least ONE gate is used (on pins 1&2) and the output of pin 2 go to the pin 20 of the RAM, wich seem to be /CS. I cannot see what is input on pin 1. Also it don't see that there is any input to pin 3 and 5 (I'm unsure) and pin 9, 11 and 13 are grounded. All outputs have only tracks leading outise of the board, but I don't see any significant use of any other output than pin 2.

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PostPosted: Sun Oct 29, 2006 5:38 pm 
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I looked at the MMC1 pinout on Kevtris' site, and the WRAM enable pin was labeled "WRAM CE" and not "WRAM /CE." I don't know if it's a typo or if the output is high for WRAM accesses. If it's the latter, then (assuming my understanding of the hardware is right) it would need to be inverted before entering the WRAM chip as /CS.


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PostPosted: Sun Oct 29, 2006 11:30 pm 
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CE is high (8kB SRAMs have separate low and high enables). Presumably it would be safer during the startup state.


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PostPosted: Mon Oct 30, 2006 5:07 am 
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This is a shame, beacause this make the task to create a SXROM by modifing a standard SNROM a lot harder. Normally, you could just disolver the 64k SRAM chip and replace it with the 256k one, by changing a few connexions.
Looking at the chips pinout :
Code:
EDIT : Removed wrong pinout found somewhere random on the net.

Code:
05. SRAM (8KB) 6264 Pinout:

                        __  __
                   +5V |01\/28| +5V
                   A12 |02  27| /WE
                    A7 |03  26| NC
                    A6 |04  25| A8
                    A5 |05  24| A9
                    A4 |06  23| A11
                    A3 |07  22| /OE
                    A2 |08  21| A10
                    A1 |09  20| /CE
                    A0 |10  19| D7
                    D0 |11  18| D6
                    D1 |12  17| D5
                    D2 |13  16| D4
                   GND |14  15| D3
                        ------

The only modifications would be pins 1, 18, 19, 20, 21 and 26, wich would be rather easy to do. However, to invert CE, that makes the modification somewhat trickier to do.

Since it is also easy to modify a SNROM board to get a SUROM equivalent of it (by just adding one or two wires from the normal SNROM modification needed to insert standard EPROMs), it would be easy to get a board to have amazing ROM and RAM size allowing big RPGs taking advantage of MMC1's capabilities.

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Last edited by Bregalad on Mon Oct 30, 2006 10:13 am, edited 1 time in total.

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PostPosted: Mon Oct 30, 2006 9:43 am 
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the 62256 diagram there is wrong.
pins 22, 21, 20, 19, 18, 17 are incorrect.

it should be:
Code:
    +--()--+
A14 | 1  28| VCC
A12 | 2  27| /WE
 A7 | 3  26| A13
 A6 | 4  25| A8
 A5 | 5  24| A9
 A4 | 6  23| A11
 A3 | 7  22| /OE
 A2 | 8  21| A10
 A1 | 9  20| /CS
 A0 |10  19| D7
 D0 |11  18| D6
 D1 |12  17| D5
 D2 |13  16| D4
GND |14  15| D3
    +------+


That makes the mod significantly easier: bend pins 1 and 26 of the 62256 straight to the side so they don't go into the board, and hook them to the logic gates/mapper chip, so it properly banks the memory. Other than those 2 pins all pins match. If the pin 26 trace on the board doesn't go anywhere you don't even need to bend it, though bending it to the side probably makes soldering on a wire much easier.

Lord Nightmare

P.S. DanSS got an FF1+2 board and mapped out the whole SXROM mapper hookup properly, he just hasn't added it to the wiki yet iirc.

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PostPosted: Mon Oct 30, 2006 10:18 am 
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Sorry to come up with a wrong pinout. It had teach me to not take any info found on the net as accurate regardless of where it comes.
Anyway, there is still a small problems : pin 23 of 6264 it teach to be 'NC' in what I've posted, but acutally is a secondary active high CS input, that the MMC1 seems to have used rather than the classical /CE of pin 20, wich I assume is tied low on normal MMC1 carts. This bad idea from Nintendo make our life harder when trying to rewire a normal cart to support 32kb chips, unless I'm totally misunderstanding something.

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PostPosted: Wed Nov 01, 2006 8:54 am 
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I assume you mean pin 26 and not 23 of the 6264...
This makes things slightly more interesting, since we need to 'sanitize' the pinout before using it:

Code:
board holes:     62256 pins:
<A13 source>     26
<A14 source>     1
1                N/C
2                2
3                3
...              ...
19               19
20               N/C
21               21
22               22
...              ...
25               25
26               20
27               27
28               28


that oughta do it. mod requires 3 wires, for <board A13> -> <62256 pin 26>, <board A14> -> <62256 pin 1>, <board /CE (pin 26)> -> <62256 pin 20>

Lord Nightmare

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PostPosted: Wed Nov 01, 2006 9:52 am 
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Quote:
I assume you mean pin 26 and not 23 of the 6264...

Raah, this annoy me. Why am I always writing stuff down wrong ?

Quote:
that oughta do it. mod requires 3 wires, for <board A13> -> <62256 pin 26>, <board A14> -> <62256 pin 1>, <board /CE (pin 26)> -> <62256 pin 20>

Yes. In SXROM case, "board A13" would be CHR A14, and "board A14" would be CHR A15. But what about "board /CE" ? This one doesn't exist, because the MMC1 doesn't output anything for pin 23 /CE, but only for pin 26 CE. So if you do it like you said, the WRAM will be enabled when the CPU acess ROM, but disabled when trying to acess RAM. That wouldn't work of course.

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PostPosted: Tue Jul 02, 2019 1:56 am 
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Bootleg SXROM?


Attachments:
IMG_0372.JPG
IMG_0372.JPG [ 2.65 MiB | Viewed 1068 times ]
IMG_0373.JPG
IMG_0373.JPG [ 2.69 MiB | Viewed 1068 times ]
IMG_0374.JPG
IMG_0374.JPG [ 399.44 KiB | Viewed 1068 times ]
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PostPosted: Tue Jul 02, 2019 7:04 am 
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Posts: 525
Location: Poland
Quite interesting cartridge, they combined 3 MMC1 games into it, each of them using different PRG-ROM and PRG-RAM size.

Game switching occurs during reset, but it is not M2 based - they detect voltage drop (like in Atari 2600 multicarts) - 4024 is powered
from capacitor.

Each of game uses separate part of battery-backed RAM chip. Those 2x small 1.5V batts reminds me of the pirate MMC5 games. I don't know if they're recheargable, but there is 47k resistor which charges them when cartridge is powered from +5V.
74HC00 (used for inverting RAM-CE coming from MMC1) is also powered from batteries (that's why they used low power HC instead of LS).

Code:
Game             | PRG-ROM | PRG-RAM |                            Link                    | ROM-A19 ROM-A18 | RAM-A14 RAM-A13
-----------------+---------+---------+----------------------------------------------------+-----------------+---------------
Sangokushi          256k      16k      http://bootgod.dyndns.org:7777/profile.php?id=3170 |    0       0    |    0      *
Dragon Quest III    256k       8k      http://bootgod.dyndns.org:7777/profile.php?id=1527 |    0       1    |    1      0
Dragon Quest IV     512k       8k      http://bootgod.dyndns.org:7777/profile.php?id=1526 |    1       *    |    1      1


Image Image


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PostPosted: Wed Jul 03, 2019 7:26 am 
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I dump the cart with Kazzo (SOROM script). The first half of the PRG ROM was read (512kb) with DQ4(j). DQ4J ROM is identical to the original dump.


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