most efficient hardware for universal discrete board (Ax,Cx, Gx, Ux, BA & CD) mappers

[mightydidz]

Good days guys,
I'd like to improve one of my design so it may support additional mappers.
Currently I'm using a 74'161 with a 74'32 to make Ax, Cx, Gx, Ux.
With some jumpers I can also make Panesian.
I'd like to push it a little further adding mapper 152 and mapper 11.
But those requires an additional 74'161.

I'm looking for the most efficient and cheapest way to add those mappers and jumpers.
I was thinking adding an additional counter, but maybe a 8bit flip-flop or latch would do the trick?

What do you guys think would be simplest and cheapest?
Thanks for your suggestions

[mightydidz]

Mapper 11 is using a 74ls377 8bit latch for bank switch.
While bandai 152 is using 2x 74'161 counter.

Any suggestion on which is the better option to make all those mappers?

Thanks

[lidnariq]

Whichever is cheaper.

Unless you have a board that uses the other features of the 74'161 (counting, asynchronous clear).

[mightydidz]

8bit latch is a bit cheaper than 2 counters.
I don't need the other features of the counters.
(correct my if I'm wrong )

I was thinking of 74'374 which is pretty cheap.
Would cpu-r/w on CLK and /romsel on OE with a 10k pull-up would work?
I'm uncertain on which one goes where.

The eight flip-flops of the ’HC374 devices are edge-triggered D-type flip-flops. On the positive transition of the
clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.
An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or
the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Thanks

[lidnariq]

I was thinking of 74'374 which is pretty cheap.
Would cpu-r/w on CLK and /romsel on OE with a 10k pull-up would work?

No. That will latch .... probably garbage.... on any write to anywhere, not just $8000-$FFFF. R/W goes low any time the CPU writes to any address.

'374 /OE means "drive the latched signal on the output of the '374". Why would you want to only drive its output while the CPU is accessing the PRG ROM?

[mightydidz]

If I switch those two, would it work?
would it latch only $8000-$FFFF?
Since I need to drive outputs on other occasion than cup accessing PRG ROM, what signal would be better?
I only used R/W and /Romsel since those are the two used on oem cartridge with 74'161.

My design would have multiple jumpers on D and Q lines.
When I want to make Cx rom, I would solder the required one.
Same for Ux rom, soldering different jumpers would adjust D & Q lines
Etc for other mappers.

[lidnariq]

If I switch those two, would it work?

Then it would latch the data bus on every single access to the cartridge, and would only drive its outputs with the latched value to the ROM address lines whenever the NES was writing somewhere.

[mightydidz]

If I use a 74hc374, I guess I'll need additional hardware?

[lidnariq]

Correct.

[mightydidz]

Lot of hardware?
There is not a big price difference between 74hc374 and 2x 74hct161.

If I go with two counter, do I also need to add extra hardware to avoid bus conflict?

[lidnariq]

Lot of hardware?
There is not a big price difference between 74hc374 and 2x 74hct161.

Does it matter whether it's only a small amount of hardware if there isn't a big price difference?

If I go with two counter, do I also need to add extra hardware to avoid bus conflict?

... what?

Those two problems are unrelated: most discrete logic mappers don't have anything to prevent a bus conflict. ANROM is the exception, it adds an extra chip for it.

[mightydidz]

Nice to know that the bus conflict isn't an issue here, I was precisely thinking about the 74'02 onboard the anrom.

Regarding hardware, I'd like to keep as simple and clean as possible for a reasonnable price. I like the 8bit latch idea. If it's only a small amount of hardware it's not an issue I still have space available.

What do I need? Couple of gates and/or transistor?

[lidnariq]

When do discrete logic mappers latch the value?
What signals are involved?
What's the boolean logic for that?

[mightydidz]

comparing with other discrete using 74'161, only /romsel and cpu-r/w are used.
/clear is tied high and counts enable (PE and TE) are grounded.
So I guess its only used as a D type latch no counting here?

The bank select registers are $8000-$FFFF.
Famicom doesn't give direct access to A15, so I have to use /ROMSEL instead. if /ROMSEL is low, A15 and M2 are both high.
At this point, I dont know where to aim at.
If you dont mind, give me a hint or some references so I may find out by myself.

If its easier, I'll stick with two 74'161, but I'd like to learn when discrete logic latch those registers. I must be close

[mightydidz]

Is it related to being a transparent latch?
Would 74ls377 also requires additional boolean hardware?