most efficient hardware for universal discrete board (Ax,Cx, Gx, Ux, BA & CD) mappers

[lidnariq]

The '377, like the '161, has both a "clock" and a "latch enable" pin.

[mightydidz]

Interesting... So 74'377 would better suit my need than a 74'374?

Ive read a bit on discrete mappers
https://wiki.nesdev.com/w/index.php/Cat ... ic_mappers
https://wiki.nesdev.com/w/index.php/Use ... ogic_Table

Can you give me additional explanation or references please?

Thanks

[lidnariq]

Look at the wiring for CNROM.
Look at the datasheet for the 74'161.
What signal is connected to what pin?
What does the datasheet for the 74'161 say about those pins?
Is there another way to describe that situation?

[mightydidz]

Here is 74'161 pinout

Code: Select all

              .--\/--.
     /Clear --|01  16|-- +5V
      Clock --|02  15|-- CarryOut
         D0 --|03  14|-- Q0
         D1 --|04  13|-- Q1
         D2 --|05  12|-- Q2
         D3 --|06  11|-- Q3
CountEnable --|07  10|-- CarryIn
        Gnd --|08  09|-- /Load
              `------'

And here is how its connected on a CNROM

Code: Select all

              .--\/--.
        +5V --|01  16|-- +5V
    /romsel --|02  15|-- Nc
     cpu-D0 --|03  14|-- CHR-A13
     cpu-D1 --|04  13|-- CHR-A14
     cpu-D4 --|05  12|-- NC (security diode D2)
     cpu-D5 --|06  11|-- NC (security diode D1)
        Gnd --|07  10|-- Gnd
        Gnd --|08  09|-- cpu-r/w
              `------'

Since /clear is tied to +5V, Q is never reset to 0.
CountEnable and CarryIn are grounded, a low-to-high transition on Clock does not increases the value of Q by 1.
CarryOut is not connected, no cascade.
Since cpu-r/w is on /load, Q is set to the value of D on a low-to-high transition.

If I understand correctly this discrete mapper, when cpu-r/w becomes low, Q gets D value on rising edge of /romsel?
I think implementing this on a 74'377 would be a good option
Here is 74LS377 pinout

Code: Select all

     .--\/--.
/WE -| 1  20|- Vcc
 Q0 -| 2  19|- Q7
 D0 -| 3  18|- D7
 D1 -| 4  17|- D6
 Q1 -| 5  16|- Q6
 Q2 -| 6  15|- Q5
 D2 -| 7  14|- D5
 D3 -| 8  13|- D4
 Q3 -| 9  12|- Q4
GND -|10  11|- CLK
     `------'

D0-7 are copied to Q0-7 when CLK rises (0 to 1) while /WE is low.
cpu-r/w would go on pin#1 and /romsel on pin#11?
This would be the same as having 2x 74'161?
Putting configuration jumpers on D0-7 and Q0-7 would allow me to control the bank select registers, thus using the full 8bit?

[lidnariq]

Since cpu-r/w is on /load, Q is set to the value of D on a low-to-high transition.
If I understand correctly this discrete mapper, when cpu-r/w becomes low, Q gets D value on rising edge of /romsel?

Yes.

D0-7 are copied to Q0-7 when CLK rises (0 to 1) while /WE is low.
cpu-r/w would go on pin#1 and /romsel on pin#11?

Yes.

This would be the same as having 2x 74'161?

Because all the other functionality is disabled, yes.

Putting configuration jumpers on D0-7 and Q0-7 would allow me to control the bank select registers, thus using the full 8bit?

Yes.