Question about UNROM's latch

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Haruka
Posts: 47
Joined: Fri Mar 23, 2018 8:58 pm

Question about UNROM's latch

Post by Haruka » Wed Feb 17, 2021 11:26 pm

Greetings, everyone!
Long story short, I'm a little confused about UNROM's latch. From what I've learned, when data is written to $8000~$ffff (i.e. /ROMSEL is 0), the data should be latched on 74xx161. According to the truth table of 161, when pin9 is 0 and there is a rising edge on pin2, the data is latched. So I assume I should connect /ROMSEL on pin9 and CPU.R/W on pin2. But I traced a legit cart and found that they got swapped. I wonder why...
Could anyone please give me some hints? Thanks in advance!

lidnariq
Posts: 10456
Joined: Sun Apr 13, 2008 11:12 am
Location: Seattle

Re: Question about UNROM's latch

Post by lidnariq » Wed Feb 17, 2021 11:53 pm

Why do you think it should be looking for a rising edge of R/W?

Haruka
Posts: 47
Joined: Fri Mar 23, 2018 8:58 pm

Re: Question about UNROM's latch

Post by Haruka » Thu Feb 18, 2021 12:20 am

Why not? I'm not quite clear of the timing.
/ROMSEL = CPU.A15 NAND M2, and when M2 is 1, address and data on the CPU buses are guaranteed to be valid. So I assume the R/W signal must be valid only during M2 remains 1, which indicates the rising edge of R/W should be earlier than the rising edge of /ROMSEL.

lidnariq
Posts: 10456
Joined: Sun Apr 13, 2008 11:12 am
Location: Seattle

Re: Question about UNROM's latch

Post by lidnariq » Thu Feb 18, 2021 12:46 am

Haruka wrote:
Thu Feb 18, 2021 12:20 am
Why not? I'm not quite clear of the timing.
R/W is part of the address bus, as far as the 6502 is concerned.
when M2 is 1, address and data on the CPU buses are guaranteed to be valid.
No!!! This is one of the biggest sources of hardware bugs in the NES (and evidently the SNES also, and probably other 6502-based machines)

On a rising edge of M2, only the address bus is valid.
On a falling edge of M2, the data bus is also valid.


Here's a diagram of what I measured in a real NES: viewtopic.php?p=244126#p244126

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