Greetings, everyone!
Long story short, I'm a little confused about UNROM's latch. From what I've learned, when data is written to $8000~$ffff (i.e. /ROMSEL is 0), the data should be latched on 74xx161. According to the truth table of 161, when pin9 is 0 and there is a rising edge on pin2, the data is latched. So I assume I should connect /ROMSEL on pin9 and CPU.R/W on pin2. But I traced a legit cart and found that they got swapped. I wonder why...
Could anyone please give me some hints? Thanks in advance!
Question about UNROM's latch
Moderators: B00daW, Moderators
Re: Question about UNROM's latch
Why do you think it should be looking for a rising edge of R/W?
Re: Question about UNROM's latch
Why not? I'm not quite clear of the timing.
/ROMSEL = CPU.A15 NAND M2, and when M2 is 1, address and data on the CPU buses are guaranteed to be valid. So I assume the R/W signal must be valid only during M2 remains 1, which indicates the rising edge of R/W should be earlier than the rising edge of /ROMSEL.
/ROMSEL = CPU.A15 NAND M2, and when M2 is 1, address and data on the CPU buses are guaranteed to be valid. So I assume the R/W signal must be valid only during M2 remains 1, which indicates the rising edge of R/W should be earlier than the rising edge of /ROMSEL.
Re: Question about UNROM's latch
R/W is part of the address bus, as far as the 6502 is concerned.
No!!! This is one of the biggest sources of hardware bugs in the NES (and evidently the SNES also, and probably other 6502-based machines)when M2 is 1, address and data on the CPU buses are guaranteed to be valid.
On a rising edge of M2, only the address bus is valid.
On a falling edge of M2, the data bus is also valid.
Here's a diagram of what I measured in a real NES: viewtopic.php?p=244126#p244126