OUT0-2 Sync issues

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Perkka
Posts: 18
Joined: Fri Jul 05, 2019 2:29 am

OUT0-2 Sync issues

Post by Perkka » Sat Feb 27, 2021 8:16 am

I'm trying to use OUT1 as a clock to sync data and send to the expansion port.
the issue is that the OUT1 signal does very often not sync with the data signals.

It did look seemingly random but I believe it's not. It is always out of sync or in sync at the same place in the code for every restart of the console.
Out1 does sync up with some delay some of the time, and the rest of the time it is delayed by one CPU cycle which will give me incorrect data.

When I'm loading data from ROM and outputting to $4016, OUT1 delayed with one cycle.

but when using this code to send A and Y registers the data is sometimes in sync.
sendtoYM:
PHA
AND #$F0
ORA #$2
STA $4016
PLA
ROL
ROL
ROL
ROL
AND #$F0
STA $4016
TYA
PHA
AND #$F0
ORA #$A
STA $4016
PLA
ROL
ROL
ROL
ROL
AND #$F0
STA $4016
RTS


LDA #$29
LDY #$80
jsr sendtoYM


LDA #$02
STA $4016
LDA #$10
STA $4016
LDA #$22
STA $4016
LDA #$30
STA $4016
LDA #$42
STA $4016
LDA #$50
If you look at the attached image OUT1 for write's 0,1,4-10 are one CPU cycle delayed. But OUT1 for write 2 and 3 are ion sync.
Anyone that has any ideas what might cause this?
Attachments
DataLog_OUT1_syncIssues.PNG

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Quietust
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Joined: Sun Sep 19, 2004 10:59 pm
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Re: OUT0-2 Sync issues

Post by Quietust » Sat Feb 27, 2021 8:24 am

Looking at Visual 2A03, it looks like writes to $4016 only update OUT0-OUT2 when apu_clk1 is high, which is every other CPU cycle. Many things in the RP2A03 work this way, including Sprite DMA, the audio frame timer, and most of the cycle timers on the various sound channels (with the Triangle channel being a notable exception).
Quietust, QMT Productions
P.S. If you don't get this note, let me know and I'll write you another.

Perkka
Posts: 18
Joined: Fri Jul 05, 2019 2:29 am

Re: OUT0-2 Sync issues

Post by Perkka » Sat Feb 27, 2021 8:31 am

Quietust wrote:
Sat Feb 27, 2021 8:24 am
Looking at Visual 2A03, it looks like writes to $4016 only update OUT0-OUT2 when apu_clk1 is high, which is every other CPU cycle. Many things in the RP2A03 work this way, including Sprite DMA, the audio frame timer, and most of the cycle timers on the various sound channels (with the Triangle channel being a notable exception).
Is there any way to make sure that the writes happens the correct cylce?

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Quietust
Posts: 1719
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Re: OUT0-2 Sync issues

Post by Quietust » Sat Feb 27, 2021 8:43 am

Perkka wrote:
Sat Feb 27, 2021 8:31 am
Is there any way to make sure that the writes happens the correct cylce?
There's one fairly easy way - perform a Sprite DMA (i.e. write to $4014), then ensure that every iteration of your write loop takes an even number of cycles. You might also need to tweak the code between the DMA and the write loop to ensure that you get the proper starting alignment (i.e. so you don't have every write being delayed), but that should be fairly straightforward.
Quietust, QMT Productions
P.S. If you don't get this note, let me know and I'll write you another.

Perkka
Posts: 18
Joined: Fri Jul 05, 2019 2:29 am

Re: OUT0-2 Sync issues

Post by Perkka » Sun Feb 28, 2021 3:28 am

Quietust wrote:
Sat Feb 27, 2021 8:43 am
Perkka wrote:
Sat Feb 27, 2021 8:31 am
Is there any way to make sure that the writes happens the correct cylce?
There's one fairly easy way - perform a Sprite DMA (i.e. write to $4014), then ensure that every iteration of your write loop takes an even number of cycles. You might also need to tweak the code between the DMA and the write loop to ensure that you get the proper starting alignment (i.e. so you don't have every write being delayed), but that should be fairly straightforward.

Thank you. Now i can go forward. If you have any other ideas of how to sync up the cycles im all ears :)

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