NES RP2A03 Logic Threshold

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quartzhunter
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NES RP2A03 Logic Threshold

Post by quartzhunter » Sun Mar 21, 2021 5:13 pm

I figure this is probably a long shot, but it's worth asking.

I'm working on a cartridge-based synthesizer that uses a microcontroller and some logic chips. I have a 74HC573 (octal d-type transparent latch) that's connected to the CPU data bus. The CPU's R/W line is connected to a 74HC04 (hex inverter), which then is connected to the 74HC573's output enable. The thought is R/W goes high for write, that gets inverted, and then that pulls the output enable low letting the CPU read from the latch.

It seems like my current problem is that the latch output isn't enabled, and the NES never reads from the latch. I know that 74HC series inputs cannot be driven by 74LS series chips because of the voltage thresholds. I know the NES's motherboard has a couple of 74HC and 74LS chips on it. Does anyone know what the logic thresholds of RP2A03 are? Or, at the very least what the R/W signal uses for logical high? I'd check myself, but I don't have access to an oscilloscope.

EDIT: I meant R/W goes high for reading, which triggers the output enable on the latch.
Last edited by quartzhunter on Mon Mar 22, 2021 7:48 am, edited 1 time in total.

lidnariq
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Re: NES RP2A03 Logic Threshold

Post by lidnariq » Sun Mar 21, 2021 5:19 pm

quartzhunter wrote:
Sun Mar 21, 2021 5:13 pm
The CPU's R/W line is connected to a 74HC04 (hex inverter), which then is connected to the 74HC573's output enable.
Surely there's more logic? If not, how do you avoid bus conflicts all the time?
The thought is R/W goes high for write, that gets inverted, and then that pulls the output enable low letting the CPU read from the latch.
R/W is low for a write...
Does anyone know what the logic thresholds of RP2A03 are?
Approximately TTL thresholds. The leaked 2A03 document just specifies Voh≥2.4V given a load of 100µA and a supply voltage of 4.75V, and Vol≤0.4V without specifying context. I don't particularly trust these to be well-quantified.
Or, at the very least what the R/W signal uses for logical high?
The 2A03 seems to emit 4V as logic high without load, down to maybe 3.5V under some load.

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Ben Boldt
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Re: NES RP2A03 Logic Threshold

Post by Ben Boldt » Sun Mar 21, 2021 6:01 pm

lidnariq wrote:
Sun Mar 21, 2021 5:19 pm
The thought is R/W goes high for write, that gets inverted, and then that pulls the output enable low letting the CPU read from the latch.
R/W is low for a write...
The way to remember this is the '/' meaning 'active low'. The signal is literally R, /W.

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aquasnake
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Re: NES RP2A03 Logic Threshold

Post by aquasnake » Sun Mar 21, 2021 10:19 pm

HC/LS can be compatible with 5V TTL level, it may need pull up/down resistors to ensure that the logic is not disordered when power on or off.
Generally, the weak pull-up/down resistance should be 47K, the strong pull-up/down one is 10K, and the strong pull-up/down resistance can be 4.7K in the case of more bus interference
1. If the output impedance of front stage is large and the decision is fuzzy, the pull-up resistor can be added to raise the level
2. The logic device with schmitt input can also avoid the error of multiple flipping close to the threshold level

quartzhunter
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Re: NES RP2A03 Logic Threshold

Post by quartzhunter » Mon Mar 22, 2021 7:46 am

lidnariq wrote:
Sun Mar 21, 2021 5:19 pm
R/W is low for a write...
You're right, that's a typo on my part. I have it wired that R/W high enables the output of the buffer.
lidnariq wrote:
Sun Mar 21, 2021 5:19 pm
Surely there's more logic? If not, how do you avoid bus conflicts all the time?
This project is based on https://github.com/Jaffe-/NESizer2. The main difference is I'm cutting out all of the peripherals building it as a cartridge so I don't have to destroy an NES. Basically, there's an ATMEGA328P that constantly feeds the NES a STA instruction, and uses that to time when to switch out the contents of the buffer.

quartzhunter
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Re: NES RP2A03 Logic Threshold

Post by quartzhunter » Mon Mar 22, 2021 7:52 am

Ben Boldt wrote:
Sun Mar 21, 2021 6:01 pm
The way to remember this is the '/' meaning 'active low'. The signal is literally R, /W.
Good tip, thank you.

quartzhunter
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Re: NES RP2A03 Logic Threshold

Post by quartzhunter » Mon Mar 22, 2021 8:01 am

lidnariq wrote:
Sun Mar 21, 2021 5:19 pm

Approximately TTL thresholds. The leaked 2A03 document just specifies Voh≥2.4V given a load of 100µA and a supply voltage of 4.75V, and Vol≤0.4V without specifying context. I don't particularly trust these to be well-quantified.

The 2A03 seems to emit 4V as logic high without load, down to maybe 3.5V under some load.
Page 4 of this says that for a 74HC chip with a supply voltage of 4.5V to 6V, the minimum for a logical high for an input is 3.15 to 4.2V. That might be my problem. Thanks for the info!

quartzhunter
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Re: NES RP2A03 Logic Threshold

Post by quartzhunter » Mon Mar 22, 2021 8:06 am

aquasnake wrote:
Sun Mar 21, 2021 10:19 pm
HC/LS can be compatible with 5V TTL level, it may need pull up/down resistors to ensure that the logic is not disordered when power on or off.
Generally, the weak pull-up/down resistance should be 47K, the strong pull-up/down one is 10K, and the strong pull-up/down resistance can be 4.7K in the case of more bus interference
1. If the output impedance of front stage is large and the decision is fuzzy, the pull-up resistor can be added to raise the level
2. The logic device with schmitt input can also avoid the error of multiple flipping close to the threshold level
I'm not sure I understand. Do you mean adding a pull-up or pull-down resistor on the input of the inverter?

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aquasnake
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Re: NES RP2A03 Logic Threshold

Post by aquasnake » Mon Mar 22, 2021 8:41 am

quartzhunter wrote:
Mon Mar 22, 2021 8:06 am
aquasnake wrote:
Sun Mar 21, 2021 10:19 pm
HC/LS can be compatible with 5V TTL level, it may need pull up/down resistors to ensure that the logic is not disordered when power on or off.
Generally, the weak pull-up/down resistance should be 47K, the strong pull-up/down one is 10K, and the strong pull-up/down resistance can be 4.7K in the case of more bus interference
1. If the output impedance of front stage is large and the decision is fuzzy, the pull-up resistor can be added to raise the level
2. The logic device with schmitt input can also avoid the error of multiple flipping close to the threshold level
I'm not sure I understand. Do you mean adding a pull-up or pull-down resistor on the input of the inverter?
Add pull-up resistors to the 74hcxx input pins, which may not be the problem.

More likely is timing, 6502's CPU bus is different from Intel bus, decoding R/W to /rd and /we also need another m2 to gate these 2 signals.

The hardware might not work by switching iRAM through multiplexer. IRAM must be on the side of NES system always, and the stack space($100 - $1ff) required by 6502 instructions must always be accessible.

The communication protocol data can be stored in the common wram space shared with Atmega, or a dual port RAM can be selected
Last edited by aquasnake on Fri Mar 26, 2021 4:13 pm, edited 1 time in total.

lidnariq
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Re: NES RP2A03 Logic Threshold

Post by lidnariq » Mon Mar 22, 2021 10:41 am

I think you've got some unrelated problem.

For now, try feeding the 2A03 always the byte "$EA", which is a NOP, and see if the address bus just keeps on counting up. If it doesn't, then maybe you're right that you have voltage threshold problems.

quartzhunter
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Re: NES RP2A03 Logic Threshold

Post by quartzhunter » Mon Mar 22, 2021 6:41 pm

lidnariq wrote:
Mon Mar 22, 2021 10:41 am
I think you've got some unrelated problem.

For now, try feeding the 2A03 always the byte "$EA", which is a NOP, and see if the address bus just keeps on counting up. If it doesn't, then maybe you're right that you have voltage threshold problems.
I'm still reading all 0's on the data bus. On the lowest 8 bits of the address bus, I'm reading nothing but 0xFF. I know 0x00 is BRK, which as far as I can tell triggers a NMI and would fetch $FFFE and $FFFF. I tried setting my logic analyzer to have A0 take a sample when low, and it read no data.

Come to think of it, the first thing it would do is read the reset vector, which would point it to $0000, which exists in internal memory. The nesdev wiki page on power-up state states that the contents of internal memory are unreliable at power-up, so it's unlikely that it would be reading all BRK instructions, right? Interesting. I'll have to dig deep into this haha.

lidnariq
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Re: NES RP2A03 Logic Threshold

Post by lidnariq » Mon Mar 22, 2021 6:50 pm

quartzhunter wrote:
Mon Mar 22, 2021 6:41 pm
I'm still reading all 0's on the data bus. On the lowest 8 bits of the address bus, I'm reading nothing but 0xFF. I know 0x00 is BRK, which as far as I can tell triggers a NMI and would fetch $FFFE and $FFFF. I tried setting my logic analyzer to have A0 take a sample when low, and it read no data.
BRK causes IRQ, not NMI. Still, correct addresses. You've definitely got something else wrong then...

What's CPU M2 doing?
Come to think of it, the first thing it would do is read the reset vector, which would point it to $0000, which exists in internal memory. The nesdev wiki page on power-up state states that the contents of internal memory are unreliable at power-up, so it's unlikely that it would be reading all BRK instructions, right? Interesting. I'll have to dig deep into this haha.
Well, you're not working in a system with any RAM, right? You have the NES CPU in isolation and its only view to the world is the output of the 74'573. (Right??)

quartzhunter
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Re: NES RP2A03 Logic Threshold

Post by quartzhunter » Mon Mar 22, 2021 7:34 pm

lidnariq wrote:
Mon Mar 22, 2021 6:50 pm
Well, you're not working in a system with any RAM, right? You have the NES CPU in isolation and its only view to the world is the output of the 74'573. (Right??)
Nope! My goal is to get this working without requiring any modification of the NES. I’m using a donor game as a breakout board because the breakout PCB I designed is taking a while to get here, and because the CIC chip in it makes my life easier.

Hm. I had forgotten about the donor game. I disabled the ROM on it by making a tiny cut in the output enable pin on the memory mapper, and tied the output enable on the ROM high. I should double check the game too. Maybe that’s interfering.

As far as M2 goes, I assume the output is still working. The console still runs Tetris.

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Re: NES RP2A03 Logic Threshold

Post by lidnariq » Mon Mar 22, 2021 7:59 pm

quartzhunter wrote:
Mon Mar 22, 2021 7:34 pm
Nope! My goal is to get this working without requiring any modification of the NES. I’m using a donor game as a breakout board because the breakout PCB I designed is taking a while to get here, and because the CIC chip in it makes my life easier.
You definitely have to worry about bus conflicts then: the 2A03 reads from stack on reset. Don't use a 74'04 to convert R/W to /RD for the 74'573; instead just use /ROMSEL from the card edge.

Don't be afraid to use a poor man's logic tester to make sure things are changing or in the state you think they are.

quartzhunter
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Re: NES RP2A03 Logic Threshold

Post by quartzhunter » Tue Mar 23, 2021 6:30 am

lidnariq wrote:
Mon Mar 22, 2021 7:59 pm
You definitely have to worry about bus conflicts then: the 2A03 reads from stack on reset. Don't use a 74'04 to convert R/W to /RD for the 74'573; instead just use /ROMSEL from the card edge.

Don't be afraid to use a poor man's logic tester to make sure things are changing or in the state you think they are.
That makes a lot of sense... I was under the impression that the 2A03 only read the reset vector when starting up. I'll give /ROMSEL a shot. Do you have any resources that go into the boot sequence of the 2A03 in more detail than the wiki? That's what I've mainly been working off of so far. Also, that logic probe is genius! I'll definitely be making one of those tonight.

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