NES RP2A03 Logic Threshold

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tepples
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Re: NES RP2A03 Logic Threshold

Post by tepples » Tue Mar 23, 2021 6:53 am

You can use any resources that describe the original 6502, as the 2A03's reset sequence is unchanged from the authentic MOS 6502. It includes at least these cycles, as I understand it:
  1. Two reads from an unknown address, whatever voltages happened to be in the program counter at power up. The CPU ignores the read values.
  2. Three reads from the stack at descending addresses in $01xx. Much of the reset circuitry is shared with interrupt dispatch (/IRQ and /NMI) and the BRK instruction, which push the program counter and status flags to the stack. Reset overrides the writes to be reads instead. The CPU ignores the read values.
  3. Two cycles to read the reset vector from $FFFC-$FFFD. The CPU copies the read values to the program counter as if jmp ($fffc) was executed, and the I flag is set as if sei was executed.
See "Internals of BRK/IRQ/NMI/RESET on a MOS 6502" by Michael Steil and the Visual 6502 wiki.

quartzhunter
Posts: 13
Joined: Fri Jan 15, 2021 12:27 pm

Re: NES RP2A03 Logic Threshold

Post by quartzhunter » Fri Mar 26, 2021 1:08 pm

I just wanted to give an update and thank you all for your replies and help. Switching from using R/W to /ROMSEL now gives more expected results, and I can actually see the values that I'm feeding it on the address bus.

Still no sound output, but I think my issue now is stability issues with my micro controller since it's connected to the clock with quite a long, janky wire. Time to move to a PCB.

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