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PostPosted: Tue Apr 18, 2017 5:27 pm 
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Location: Poland
I mistakenly reversed connections between D0 and D2 in AY8912, so it was playin in the correct tempo but rather quite different data :D
Now its fine, however the sound still is quite out of the tune. And all can be closed in standard famicom shell ;)

https://ufile.io/vqv24

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PostPosted: Wed Apr 19, 2017 12:55 am 
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Location: Germany
I have made my own board for this as well. ;)

Untested so far cause I didn't get any FME-7/5A games yet.

I wish there was another way that doesn't require CPLD knowledge to use donors for that one. :(


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PostPosted: Wed Apr 19, 2017 5:30 am 
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Lol, so thin tracks - make them tighter before ething.

Why people have so much resistance against CPLD? They give much more control than microcontrollers - you can set up with respect to single clock cycle what is at the output. Maybe the language (VHDL) seems strange at first glance, but it is really not as bad. There are a lot of ways to express the same thing, but you can stay with one of them you are most familiar with. Bad thing is that the web has a lot of outdated info, lots of people's advices are wrong, so you have to learn all by yourself, but then you gain so much power that you dont have to be sticked any more to 74xx chips, rare ASIC chips like those mappers (FME7) or PALs - you can code everything by yourself.

It is quite rare to find 5 V tolerant CPLD/FPGA nowadays, but 74LVC245 buffer costs 0.1$/piece. Is is is smd (so20), so no drils need to be done. Every input is at opposite side to the oputput so really almost zero effort in routing tracks. All you need is 3.3V low dropout regulator (LM1117-3.3 works well). You can but cheap CPLD starting from 1$.
And you can implement FME-7/VRC6/VRC4/VRC2 or almost any mapper inside (except MMC5 which need external RAM and most of cheap CPLDs don't have extra logic for ram inside).

Don't be ashamed ;)

BTW. I saw one guy tried to encode MMC1 in PAL. He used 4 PALs. Maybe good for learning how to create extra-optimised logic, but from economic point - nonsense.
I have succesfully impkemented MMC1+MMC3+some other mappers AT ONCE in this 1$ CPLD.


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PostPosted: Wed Apr 19, 2017 6:01 am 
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Doesn't working with CPLDs and VHDL require proprietary software with fiddly license management rigamarole? I know developing new mappers for the PowerPak's FPGA does.


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PostPosted: Wed Apr 19, 2017 6:16 am 
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Both Quartus (for Altera) and ISE Webpack (Xilinx) are free to download and they can generate output files without any restrictions. As far as I remember you need to get licence file from the website, but is is free and fully automatic process which takes less than 1 minute.


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PostPosted: Wed Apr 19, 2017 7:35 am 
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krzysiobal wrote:
Both Quartus (for Altera) and ISE Webpack (Xilinx) are free to download and they can generate output files without any restrictions.

Not even a restriction that your PC must run Windows, as opposed to a competing operating system? (I checked, and Linux is available now, but macOS and FreeBSD aren't.) Or be x86 or x86-64, as opposed to a competing architecture?

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As far as I remember you need to get licence file from the website, but is is free and fully automatic process which takes less than 1 minute.

Perhaps this is PowerPak-specific, but Xilinx likes to drop its older FPGAs from the currently available versions of the program and key generator.


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PostPosted: Wed Apr 19, 2017 5:56 pm 
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This doesn't even go into the malware they call protections. XD

This is why you have a specific hard drive or even better, machine, for this. This way you don't get burned by the likes of Intuit's TurboTax back in the day. I wouldn't put it past them to try to mess with your EFI firmware.

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Fail, fail, fail again. Keep trying, then maybe this damn thing will work. Eventually you might even know why it worked.


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PostPosted: Wed Apr 19, 2017 6:08 pm 
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tepples wrote:
Doesn't working with CPLDs and VHDL require proprietary software with fiddly license management rigamarole? I know developing new mappers for the PowerPak's FPGA does.


Yeah it can be annoying when designing for decrepit device that's no longer supported and may have required a non-free license when it was supported. Designing for discontinued devices is always going to require you to jump through extra hoops, that's not limited to programmable logic toolchains.

Xilinx, Lattice, and Altera all offer free licenses that are easy to manage. High end premium devices may still require a paid license, but there's no realistic reason to put that scale of a device in a cartridge.

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PostPosted: Wed Apr 19, 2017 10:07 pm 
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AFAIK, the iCE40 is the only FPGA that can be fully reverse engineerable at this point. Encryption and such have been tampered with, documentation all public.

http://www.clifford.at/icestorm/


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PostPosted: Thu Apr 20, 2017 5:26 am 
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krzysiobal wrote:
Lol, so thin tracks - make them tighter before ething.


I see no reason to laugh at this since your traces are the same width. My power traces are thick enough and I've made many boards this way. All of them work flawless without any problems. :)

Anyway, as for CPLD programming. I lack knowledge of VHDL nor do I want to buy any licenses or get any licenses for a software, neither do I plan to get new equipment for just 1-2 projects. ;)

If I were to work alot with VHDL I can understand the need of it but for now, nah.


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