How to designs NES ON FPAG

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xyzgto
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How to designs NES ON FPAG

Post by xyzgto » Tue Aug 19, 2008 12:06 am

I uses develop version: XILINX SPARTAN- 3E STARTER KIT

How does want NES puts up go?

There is at want before me, Seek NES IC, Its IP at goes use procedure DUMP out,

Does not know he IC is what, Too has no DUMP procedure, Can someone help I?

Sorry, My English not very good, This is use translate software turn over become English

sleepy9090
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Post by sleepy9090 » Fri Aug 29, 2008 3:26 pm

i just bought one of these, lets figure it out?

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kyuusaku
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Post by kyuusaku » Fri Aug 29, 2008 5:10 pm

There's no way to "dump" the IP from the NES CPU and PPU, you're on your own to reimplement all the logic either from reverse engineering or by gaining access to Nintendo secret files. I'm also developing a FC clone using a Spartan 3E in mixed schematic entry and Verilog based off Nesdev documentation. Maybe I can help with some FPGA pointers but I'm not interested in working in a team project with this, the IP is too valuable.

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MottZilla
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Post by MottZilla » Fri Aug 29, 2008 5:48 pm

Gonna make your own Famiclone and make millions? ;)

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kyuusaku
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Post by kyuusaku » Fri Aug 29, 2008 6:56 pm

One can dream ;) But there is still a lot of $$$ to be made from Famiclones, I'm guessing especially ones with 720p/1080p output or other trendy features.

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Bregalad
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Post by Bregalad » Sat Aug 30, 2008 1:36 am

Gonna make your own Famiclone and make millions? Wink
When I'll have finished my studies in electronics engineering I could definitely do something like that. Now that the pattent have expired for the NES I guess this is legal (even if the official patents are inacurade, which is cheat from Nintendo).

Anyway Kevin Horton was the first to sucessfully did something like that.
Useless, lumbering half-wits don't scare us.

tepples
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Post by tepples » Sat Aug 30, 2008 6:33 am

kyuusaku wrote:One can dream ;) But there is still a lot of $$$ to be made from Famiclones, I'm guessing especially ones with 720p/1080p output or other trendy features.
The NES architecture assumes 240p output. I can see a few advantages of 480p or bigger output:
  1. emulating more than one NES at once,
  2. a hint screen displayed above the game window like in PlayChoice,
  3. less lag from typical entry-level flat TVs' upscalers, and
  4. the possibility of Scale#x or hq#x output.
But I'm not sure that those features can easily fit onto an affordable FPGA.

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MottZilla
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Post by MottZilla » Sun Aug 31, 2008 11:58 am

Any Famiclone that actually does sound and video and many other things right that all the Famiclones FAIL at would be nice. It's a shame the market is stuffed full of shitty NES clones as many average users will think there is nothing wrong when there is so much wrong.

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kyuusaku
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Post by kyuusaku » Fri Sep 12, 2008 5:22 pm

Little bump..
MottZilla wrote:Any Famiclone that actually does sound and video and many other things right that all the Famiclones FAIL at would be nice. It's a shame the market is stuffed full of shitty NES clones as many average users will think there is nothing wrong when there is so much wrong.
It will be VERY hard for me to get that accurate, at least for a long time. The clones actually are clones afterall, they just have a few sloppy parts probably from mistakes viewing the mask.

Right now my clone doesn't really even have a CPU yet, just someone else's HDL core I haven't tested as a placeholder. Currently I'm working on the PPU so I can hit the ground running. I've got a prototype for all the components designed except for sprite evaluation, I just need to put it all together and design a basic upscanner to see some results..

I think also if things work out I can use my design to write a visual tech document, like a more accurate update to Brad Taylor's and integrate newer info from the forum.

CartCollector
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Post by CartCollector » Sat Sep 13, 2008 12:03 pm

You almost have the PPU done? You should make a board that can be put in to an NES to replace the normal PPU and output multiple video formats. Like have one board with RGB and Component and another with S-Video and composite. The S-Video/composite board should have the color carrier rotate 180 degrees every scanline and switch off every frame, for example:

Code: Select all

   Scanline:      Odd    Even    
 Odd Frames:       0      180
Even Frames:      180      0
I don't think the NES already does this (someone correct me if I'm wrong).

Also, it should have the luminance and chrominance signals filtered before they are combined to form the composite output.

If you don't understand what I'm getting at, let me know.

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kyuusaku
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Post by kyuusaku » Sat Sep 13, 2008 1:52 pm

I think plopping the FPGA into a NES would be far too difficult/time consuming/expensive, I'm going to keep it all on my development board. I have also thought of composite and S-video, but that's quite a long way ahead... First I'll have to look into the possibility of generating S-video with the original method.

lidnariq
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Post by lidnariq » Sun Sep 14, 2008 10:41 am

CartCollector wrote:The S-Video/composite board should have the color carrier rotate 180 degrees every scanline and switch off every frame
That's actually the point of 20th scanline being short by one pixel. (I'd point you at the wiki but it's down for me).

It doesn't always look good, though -- especially with scrolling content. (The last time I played with a modern ATI card's composite/s-video out, it included a bunch of different color modulation options because different pictures look better with different characteristics).

Stief21774
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Post by Stief21774 » Sun Sep 14, 2008 3:11 pm

A few months ago, I tried to make a NES in VHDL/Verilog, and run it on a Virtex-II PRO development system from Digilent. I was sucessful in playing donkey kong on it (without audio).

I recently started working on it again. I'm trying to pipeline the PPU, and implement audio.

kyuusaku: I am also using someone else's CPU. I got mine from www.birdcomputer.ca. After through testing, I only found one small bug involving the RTI instruction. I've been meaning to e-mail them to get it fixed and just haven't gotten around to it yet.

I like your idea about creating a new tech document. All of the documents I've found have been incomplete and a few even contradict each other.

-Kenny

CartCollector
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Post by CartCollector » Sun Sep 14, 2008 4:28 pm

The S-Video/composite board should have the color carrier rotate 180 degrees every scanline and switch off every frame
That's actually the point of 20th scanline being short by one pixel. (I'd point you at the wiki but it's down for me).
Actually, being short by one pixel only rotates the phase by 240 degrees, not 180, since the CPU and the color carrier oscillate at a ratio of 2 color carrier cycles to 3 PPU cycles. 3.58/5.37 = 2/3. (2/3)*360 = 240. Visually:

Code: Select all

Original color carrier:
				---   ---   ---   ---
				   ___   ___   ___   ___
CPU clock:
				--  --  --  --  --  --
  				__  __  __  __  __  __
Color carrier -1 CPU cycle:  
(4 dashes)
				-   ---   ---   ---   --
				 ___   ___   ___   ___  

Original color carrier:
(again)	  ---   ---   ---   ---
				   ___   ___   ___   ___
Notice how the original and phase-shifted color carriers' clock edges do not exactly match up.

Look at Nestopia with the NTSC filter on and you'll notice that color and luminance decoding errors are still noticeable on still images, which they wouldn't be if the phase rotated by 180 degrees. For instance, if one white pixel surrounded by black pixels created interference in the chroma bandwidth that caused it to be yellow tinted, it would be blue tinted in the next frame if the color carrier shifted 180 degrees. Since yellow and blue are exactly opposite each other, when averaged out by flickering, the pixel looks colorless (white). However, if the color carrier shifts 240 degrees, the pixel would be cyan tinted in the next frame, and would look light green tinted when averaged out.

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kyuusaku
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Post by kyuusaku » Sun Sep 14, 2008 5:22 pm

Stief21774 wrote:I got mine from www.birdcomputer.ca. After through testing, I only found one small bug involving the RTI instruction. I've been meaning to e-mail them to get it fixed and just haven't gotten around to it yet.
Good to hear because that's the one I'm going to test my PPU with! ;)

BTW, I'm using a Digilent Nexys 2 + breadboard for I/O.

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