It is currently Mon Oct 23, 2017 1:49 pm

All times are UTC - 7 hours





Post new topic Reply to topic  [ 28 posts ]  Go to page Previous  1, 2
Author Message
 Post subject:
PostPosted: Mon May 04, 2009 6:10 am 
Offline
User avatar

Joined: Tue Apr 07, 2009 9:20 am
Posts: 20
Quote:
if ((prgrw_in = '0') AND (prgce_in ='0')) then


You're right, it does make a lot more sense this way - much less prone to mistakes.
Unfortunately I don't think I could possibly try anything I haven't before (for the shift register / input process), and with the same black screen for everything it's gotta be something else - I should've at least seen something on the screen once by now.
Maybe I've made a mistake on the bankswitching -- possibly the CHR side of things? I haven't changed that since the original code in the first post.


Top
 Profile  
 
 Post subject:
PostPosted: Mon May 04, 2009 9:03 am 
Offline

Joined: Tue Aug 07, 2007 10:28 am
Posts: 95
Are any of your bus's bidirectional?


As a test, couldn't you use a simple game that doesn't use any mapper chips to at least see if the system is running with this logic in your CPLD.


Top
 Profile  
 
 Post subject:
PostPosted: Tue May 05, 2009 9:04 am 
Offline
User avatar

Joined: Tue Apr 07, 2009 9:20 am
Posts: 20
None of my buses are bidirectional (thru the PLD, anyway). Other games (NROM, CNROM, and UNROM) are all working fine with this CPLD software, so I know the CPLD is working.

Here's something that's kind of confusing me though, I pulled out a logic analyzer and took a look at the M2, /CE, R/W, D0, D7, A13, and A14 pins. I managed to track down the Reset write, the Reg3 writes, and the Reg0 writes - at least I think I did. They're not quite what I expected. A write kinda looks like this (I'm gonna try to ACII this):

M2: 0______1----------------0________

/CE: 1----------0____________1---------

R/W: 1--0______________________1---

And as much as I tried, there is NEVER a rising edge of M2 while /CE is low. Or, is this waveform just wrong?


Top
 Profile  
 
 Post subject:
PostPosted: Tue May 05, 2009 10:06 am 
Offline
User avatar

Joined: Mon Sep 27, 2004 2:13 pm
Posts: 1667
Location: .ma.us
The waveform is correct because "/CE" is "M2" NAND A15. It shouldn't be treated as /A15.

As for how data is valid at the rising edge of "M2", well the data output latch is enabled throughout "M1", but its tri-state buffer is enabled at "M2" && /RW (but /RW was predecoded through "M1".) With the propagation of input buffers, data arrives before/at the rising edge. Datasheets won't tell you this, but it can be observed by crosschecking the only accurate 6502 diagram: http://www.weihenstephan.org/~michaste/ ... 2/6502.jpg with the schematic: http://www.shiresoft.com/downloads/docs/6502.pdf .


Top
 Profile  
 
 Post subject:
PostPosted: Tue May 05, 2009 10:36 am 
Offline

Joined: Tue Aug 07, 2007 10:28 am
Posts: 95
I'll have to respectfully disagree about data on the rising edge of M2.

I'll use these as my sources:

http://www.atarimagazines.com/computeii/issue1/page9.php
Specifically, Figure. 1 and the paragraph below.

Datasheets, this one and the other ones on the 6502.org site.
http://6502.org/documents/datasheets/synertek/synertek_hardware_manual.pdf

I'm not sure why datasheets are not valid as they specifically say when devices can guarantee data to be valid from the CPU.

I hope others could respond as we could go back and forth on this forever.




Also, kathaku I wasn't talking about the CPLD not working. Just not working when the MMC1 load is in it. Try loading CPLD with the MMC1 code while using a non MMC1 game that doesn't use any kind of mapper chip. The game should still run correctly, right?[/url][/quote]


Top
 Profile  
 
 Post subject:
PostPosted: Tue May 05, 2009 10:45 am 
Offline
User avatar

Joined: Tue Apr 07, 2009 9:20 am
Posts: 20
Okay here's a better waveform to look at. This is what I thought was a write to Reg0.
Image
So if the data is ready on the rising edge of M2, then D7 is a 1, but if it's on the falling edge of M2, then D7 is a 0. I thought it would've been the falling edge, because on the rising edge D7 is always 1.

I could've made a mistake, when I get home tonight I'll try again.


Top
 Profile  
 
 Post subject:
PostPosted: Tue May 05, 2009 2:17 pm 
Offline
User avatar

Joined: Mon Sep 27, 2004 2:13 pm
Posts: 1667
Location: .ma.us
2600 wrote:
I'm not sure why datasheets are not valid as they specifically say when devices can guarantee data to be valid from the CPU.

I'm not denying that it's most proper to use the falling edge, just pointing out that designs have had success with the rising edge. If data wasn't arriving in time, lots of designs out there wouldn't work, but they do. I don't think the PowerPak has any input delays on the line, but that would be the first thing to check in the constraints file.

I really think the datasheets should be taken with a few lumps of salt, they significantly oversimply the internal workings and the timing doesn't necessarily reflect the 2A03's process.


Top
 Profile  
 
 Post subject:
PostPosted: Wed May 06, 2009 9:05 am 
Offline
User avatar

Joined: Tue Apr 07, 2009 9:20 am
Posts: 20
Quote:
we could go back and forth on this forever


Although I have yet to make this mapper work with my PLD, I have learned enough to know much more clearly what is going on. I figure the problem is now something that can be solved with some simulation.

Thanks to everyone who's helped me out with this - and when it does work, I'll post my working code for all.


Top
 Profile  
 
 Post subject:
PostPosted: Thu May 07, 2009 5:54 am 
Offline

Joined: Tue Aug 07, 2007 10:28 am
Posts: 95
You know it is kinda interesting that you are having trouble with MMC1 on your board. The FunkyFlashCart had trouble with MMC1 as well. I don't think that was ever fixed though.

Good luck it will be interesting to see what you find.


I'd have to look up more detail of the mapper, but I wonder if you should clear q_s when the count is 5 as well. I also wonder if checking if count is = to 5 should be in a separate process and synchronize it to M2, but use the opposite M2 polarity of when you clock the data in. That way there would be a little delay to clock the data in correctly before you transfer it.


Top
 Profile  
 
 Post subject:
PostPosted: Fri Mar 30, 2012 5:01 pm 
Offline

Joined: Sun Jun 12, 2011 12:06 pm
Posts: 225
Location: Poland
Quote:
prg_addr_out(17) <= R3(3) OR prg_addr_in(14);
prg_addr_out(16) <= R3(2) OR prg_addr_in(14);
prg_addr_out(15) <= R3(1) OR prg_addr_in(14);
prg_addr_out(14) <= R3(0) OR prg_addr_in(14);


What if you burn for example a PRG ROM that is 128KB of size
and the prg_addr_in(14) would be '1'?
It will make the cpu read at the place that it is not programmed.

The quote in MMC1 specification is that it must be the last bank - the last one that is burned on the ROM (or maybe you will be playing with grames with 256KB of PRGROM only?)


Top
 Profile  
 
 Post subject:
PostPosted: Fri Mar 30, 2012 5:21 pm 
Offline

Joined: Sun Jun 12, 2011 12:06 pm
Posts: 225
Location: Poland
Just minute ago I succesfully ran version of MMC (I had some problems during last hours).
It is basically very similar to yours instead of the one thing that I mentioned.

The next difference is that I init the R0 with 01100 and R1,R2,R3 with 00000

I am not using variables.


Top
 Profile  
 
 Post subject:
PostPosted: Fri Mar 30, 2012 5:45 pm 
Offline

Joined: Sun Sep 19, 2004 11:12 pm
Posts: 19122
Location: NE Indiana, USA (NTSC)
krzysiobal wrote:
What if you burn for example a PRG ROM that is 128KB of size
and the prg_addr_in(14) would be '1'?
It will make the cpu read at the place that it is not programmed.

Ground unused upper address bits when soldering the memory to the board.


Top
 Profile  
 
 Post subject:
PostPosted: Sat Mar 31, 2012 8:14 am 
Offline
User avatar

Joined: Sat Feb 12, 2005 9:43 pm
Posts: 10067
Location: Rio de Janeiro - Brazil
Or program the same data repeatedly until it fills the chip so that the upper bits of the address won't matter. If you're not making a permanent cart (i.e. it's a devcart and you want to be able to run 256KB games as well as 128KB ones without hardware modifications), this is the better option.


Top
 Profile  
 
Display posts from previous:  Sort by  
Post new topic Reply to topic  [ 28 posts ]  Go to page Previous  1, 2

All times are UTC - 7 hours


Who is online

Users browsing this forum: No registered users and 5 guests


You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Search for:
Jump to:  
Powered by phpBB® Forum Software © phpBB Group