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PostPosted: Sat Sep 03, 2011 11:35 pm 
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So the project has officially be accepted by my department at school there is a little blurb about the project. I've been slacking on posting up our progress so you'll have to excuse the large post to attempt to catch up.

The post to do with initial planning is here.

So instead of making separate posts for each little thing that comes up I'll try to keep everything in this post for now.

For the most part we've been spending the summer playing around with the kazzo considering using some variant of it to program the onboard memory with an onboard AVR mcu. But really we won't need to be as versatile as the kazzo since I would like the reading/writing of the all memory via USB to be independent of whatever mapper is currently loaded on the CPLD.

We've also played around with an NROM dev cart, gotta start somewhere, may as well be something with no mapper :) Used the ReproPak, with some modifications to allow for battery backing the SRAM used. Thing I found out that seemed a little backward to me. He ties the PRG memory's /CE to ground and has PRG /CE driving the /OE. Wouldn't be a problem generally, but since we were using the kazzo to program the memory, having it constantly enabled proved to be a problem since kazzo ties the PRG and CHR busses together. So we just cut the ground on /CE and have /OE and /CE tied togther. The battery back up circuitry is the same as most NES carts, but we had to add pull up resistors on the /CE lines to prevent from draining the battery. Two of the switches in the top control whether the /WE signal is controlled by the cart edge or tied to Vcc for write protection. That was the only way we could find to keep the data from being corrupted everytime. One switch was for mirroring and the other for PRG ROM size 16KB/32KB selection. Everything is in working condition now, but I've got some bug that causes the first byte in CHR to always be programmed to 0xA0 vice 0x00. Not sure why, think it's the kazzo, but I was able to write my one program for the kazzo to load up via bootloader and write it back to 0x00 after everything else was programmed.

Image
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Last weekend I made up what I like to call the "NES protoboard" I've seen a similar idea mentioned before I think it was Memblers. But basically the board holds the PRG, CHR, And WRAM and routes any signal that may be used or controlled by a mapper to the back of the board where I'll be using some female header to connect up the CPLD. But since I had a little space I found some room for things that could possibly be used. The only things I didn't route to the back end were the lower address byte of CHR. But I do have some extra pads on the outer "wing" area that anything could be routed to by hand.

I added some other bells and whistles because they seem to frustrate me commonly. One being mounting the board to the back shell of a cart. That's where I made those little tabs on to allow the board to be screwed to the cart plastic bottom securely without needing the top shell that wouldn't fit anyways.

I also extended the cart edge pins INTO the actual case because if/when you want to tap off of them they're actually outside of the case housing and soldered wires could interfere with a connector potentially without my exteneded pins.

The only thing that changes from flash/EPROM/EEPROM/SRAM whatever is the upper address bytes and control signals. Those are conveintly controlled by the mapper generally speaking so they all got sent to the back of the cart. Because of this my protoboard could accept most any memory in a DIP package.

I've also provided battery backup circuitry and each memory has it's power selectable by solder bridge. May also prove prudent if the cart is powered via USB to prevent attempting to powering the NES through the cart connector.

Here's the schematic and pcb files including the cart connector and other items I've had to create for the library. I've designed everything using
DesignSpark which is free and pretty easy to learn in my experiences thus far.

Here's a preview, I should have them in next week.

Image
There's nothing actually over the connector, it just defaults user created items to that 3d rendering height...
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Image

Our goal over the next month before school and the project officially start, is to get a simple "discrete mapper devboard" working. We're hoping to support N/A/U/BNROM etc and program it with the kazzo. We'll be able to connect up our little 72 macrocell CPLD to the NES protoboard and test out some designs from Xilinx IDE we've started designing.


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PostPosted: Mon Sep 05, 2011 4:07 am 
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Took the first step with a CPLD on the NES tonight. Replicated the UxROM mapper with Xilinx schematic and programmed it on a CPLD devboard. Just tested it out with a standard board with EPROMs and the '32 and '161 removed. Next up is to upgrade the NROM devboard and test out flashing the cart. Then we'll try out some other mappers.

Here's some pictures
Image

Much better than those two little DIPs :)
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PostPosted: Thu Nov 24, 2011 7:25 pm 
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Apologies, for the lack of updates as of late. Not certain how many people are still interested in the project, but things are still moving forward. Most of our time spent working on the project was in the form of papers required for the first term which happens to be a writing intensive course...

We've been posting everything formally here as is required for school credit. If you snoop around there are block diagrams and such.

Now that most of the writting/research is done we're working on the final design for the next 2 weeks. For the most part I've narrowed it down to using a Lattice CPLD (Mach Xo2 with 640 Mcells) because of the excessive capabilities it has compared to it's Xilinx/Altera equivalents while at a lower price. I'm tring to determine which mcu to use now and am considering the atmega325A and atmega128A. They are nearly pin compadable with the exceptions being USB and I2C pins. The atmega325 would do the trick for the project, but the 128 may be more desirable it were ever used as a coprocessor for the NES (which is a little outside the scope).

Because the CPLD is so massive I'll be using it to io extend the mcu and a mapper on the same flash. I would really like to get all discrete mappers, MMC1 and MMC3 in the CPLD at the same time. Allowing the mcu to select the desired mapper without reflashing the CPLD.

We're looking at 512KB of PRG/CHR memory in the form of SRAM, 32KB WRAM, and potentially an extra 512KB of PRG-ROM.

The goal is to allow the rom to be programmed to the cart while connected to the NES by "removing" it from the NES with level shifting buffers for the whole 72 pin connector. Satisfying the ultimate goal of quick and non-cumbersome programming which current solutions lack.

Total cost of components is still less than $50. PCB and case costs vary heavily depending on needs.

I'll be posting up the final design once it's complete next weekend. If anyone has inputs I'm more than willing to hear them out, but I can't really consider large changes at this point... Specifically any input on mcu/CPLD/memory connections and capabilities are open for modifications in the next week.


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PostPosted: Sun Nov 27, 2011 4:34 am 
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I'm interested in how this goes. Like I mentioned previously, it's sorta like a board I want to make eventually, with a Spartan3 FPGA and PIC32 MCU (both are 5V tolerant). It's pretty damn cool to see new NES boards with this kind of stuff on it, yours would be the most advanced to date.

I looked at that Mach XO2, sounds pretty nice!


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PostPosted: Sun Nov 27, 2011 5:30 am 
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I appreciate the feedback. At times I feel like the project is a bit overboard, and I question if any of the features I'm trying to provide will actually be exercised. But in reality I'm setting it up to be more than just a ROM/game development cart, but a hardware development board too. So I guess that gives the broad scope some justification.

I agree it is always fun to see these new parts connected up to the NES, I don't think that'll ever get old :)

Yeah that XO2 man, the only downer is it's not 5V tolerant. We had been planning on using a 9500 series Xilinx to stay 5V tolerant. But we decided to just level shift everything for other reasons and now the XO2 is too tempting to pass up with it's size, cost, and all the hardened features of SPI, I2C, Flash, Dual ported RAM, etc, etc...

The idea would be that you could design a mapper with the Dev cart for another CPLD though that may be 5V tolerant atleast. Even if it weren't though and a game was actually produced with the XO2, the requirement to level shift isn't nearly as bad if you've defined all your signals you would only need a few extra cheap ICs for level shifting if you kept 5V memory. But with all the signals undefined essentially it was easier to just level shift everything on the way into the cart and gain the benefit of 3.3V for everything on board.


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PostPosted: Sun Nov 27, 2011 8:07 am 
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Just caught wind of this. Awesome project!


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PostPosted: Fri Jan 06, 2012 12:27 am 
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So most things are pretty well laid out for this thing now. If anyone's curious of specifics for the design we had to post everything up here: http://beaversource.oregonstate.edu/projects/44x201109

My goal has kind of transformed to allow for a lot of capability and functionality. If I've seen a mapper idea mentioned recently I've noted it and tried to provide the hardware required to make it possible. The parts cost is around $50 right now for individual quantities. If it ever actually gets produced it should be able to stay under $100 as hoped.


Highlights:

512 KB of PRG and CHR SRAM
512 KB of PRG Flash
32 KB of WRAM
possibly some extra serial eeprom tossed on because it's cheap

Atmega325
Mach X02 644 MCell CPLD

entire board is level shifted to 3.3V as the signals enter the cart. This also allowed for the cartridge to be "removed" from the NES for programming. The main goal was to be quick and convenient to program. So assuming your PC is close enough for a USB cable to reach you can leave everything plugged in from one build programming to another. You should be able to leave the power on as well you'd just have to hit reset after programming (the NES would freeze up during programming unless you kept it running off internal RAM for some reason).

USB read and write access to ALL memories on board, and should be able to reconfigure the CPLD as well via USB (flash configuration on CPLD provides over 100K write cycles). I ran a quick demo of programming 8KB of SRAM in under a second with a prototype of our firmware and software. Picture below and quick video here: http://www.youtube.com/watch?v=jYlYKQpxwA4&context=C3dc84ddADOEgsToPDskLuEW6BpKAuzi5yxhSsTajc

[EDIT: image attached]

I calculated it out to run about 40KB/sec for this setup. The final one will be a little different. But at that speed most games program around 10sec and all memory space on board could be programmed in 20+ seconds.

But the CPLD is sort of dual functioned. It I/O extends the mcu durring programming and also runs as the mapper during play/testing. Since the CPLD was fairly large we were able to do this to keep chip count and part cost down.

I've got nearly every pin connected to the CPLD. So all PRG addresses can be decoded and optionally all CHR as well. I've left some of this configurable for the time being with jumpers because I started to run out of I/O on the CPLD. So It's possible to get as low as 128byte banks on CHR memory but at a cost of not having lower CHR address bits as inputs. 128byte pages gives you down to A6, 256byte to A5 etc.

I had planned for 8KB PRG bank switching but I was wondering if anyone can think of a benefit to less than that? I can't think of any and the I/O seemed more useful for decoding all PRG addresses for things such as dec $4011 and such.

The CPLD is what I think I'm most excited about though. I discussed it above but it's stuffed with goodies. Lots of capabilities with the Dual ported SRAM, and other hardened features without the cost of logic elements. It opens the door for using the mcu as a co-processor and everything possible there. It's not as cheap as some CPLD's but still reasonable to put in a production cart. It has a LOT more to offer than a $4-5 CPLD but at about twice the cost.

I don't think it would ever be that reasonable to produce a game that made use of everything on board. But reading through some of the old posts everyone has their own ideas of what they'd like. I tried to remove limitations where possible with the thought that limitations could be placed by the user in a final production.

I kind of think my goals are a bit lofty at times, but I'm having fun working on it and getting school credit at the same time so either way I win :)

Next steps are to port the firmware from the atmega8 in the demo to the kazzo and do some testing with the NESprotoboard. Should be ordering the prototype and parts within a month.


Attachments:
IMG_3936.JPG
IMG_3936.JPG [ 65.91 KiB | Viewed 893 times ]


Last edited by infiniteneslives on Tue Feb 06, 2018 2:20 pm, edited 2 times in total.
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PostPosted: Fri Jan 06, 2012 2:35 am 
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NSFs use 4KB PRG banking. Musicians would definitely be interested in a cart they can use for performances with that fast uploading.


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PostPosted: Fri Jan 06, 2012 3:42 am 
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bunnyboy wrote:
NSFs use 4KB PRG banking. Musicians would definitely be interested in a cart they can use for performances with that fast uploading.


Thanks for that info, I had originally planned that PRG A0 would get lost as in input if one wanted 4KB banks for PRG ROM. But I think I'll make it the default to have 4KB banks and all PRG address inputs then. I might make it so you can't have CHR A0 and PRG A0 at the same time instead.

I've talked a bit with Andy over at http://www.batslyadams.com/ (floats around nesdev a bit too) he's pretty involved with the music scene. I'll have to check back in and see if he has any last minute inputs.


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PostPosted: Fri Jan 06, 2012 1:12 pm 
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infiniteneslives wrote:
bunnyboy wrote:
NSFs use 4KB PRG banking. Musicians would definitely be interested in a cart they can use for performances with that fast uploading.


Thanks for that info, I had originally planned that PRG A0 would get lost as in input if one wanted 4KB banks for PRG ROM. But I think I'll make it the default to have 4KB banks and all PRG address inputs then. I might make it so you can't have CHR A0 and PRG A0 at the same time instead.

I've talked a bit with Andy over at http://www.batslyadams.com/ (floats around nesdev a bit too) he's pretty involved with the music scene. I'll have to check back in and see if he has any last minute inputs.


Then it would be a totally different mapper than FME-7/SS-5b, because it is not backwards compatible.

Since you are changing it, Maybe you can make it backwards compatible by making a new mapper revision to use a MODE for PRG bank size.

for this mode you can add in another port to write in at $A000 as Port $10 (%0001xxxx).

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PostPosted: Fri Jan 06, 2012 3:30 pm 
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Hamtaro126 wrote:

Then it would be a totally different mapper than FME-7/SS-5b, because it is not backwards compatible.


The mapper isn't intended to be anything concrete. The goal is for it to be something that can be reprogrammed over USB as well.

But since the mapper is pretty big do plan to make some mappers that are selectable. For instance an "all-in-one" that would contain all the discrete mappers on one CPLD configuration. Then the user can select which one to use when programming or by having the hardware decode the mapper number from the .nes file header.

So it's possible one could make a FME-7 mapper with selectable bank size like your saying, I just don't think it'll be the default configuration.


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PostPosted: Fri Jan 06, 2012 6:48 pm 
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Okay, That makes sense then.

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PostPosted: Tue Jan 31, 2012 5:11 am 
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Some previews of the PCB. We're ordering tomorrow hopefully, getting excited to see it all together.

I now know why they made NES carts so huge... :)

[EDIT: images re-attached]


Attachments:
File comment: 3d render bottom
nesdev_3d_bottom.jpg
nesdev_3d_bottom.jpg [ 278.59 KiB | Viewed 893 times ]
File comment: 3d render top side
nesdev_3d_top.jpg
nesdev_3d_top.jpg [ 266.48 KiB | Viewed 893 times ]


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PostPosted: Thu Feb 02, 2012 1:54 pm 
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Looks great! What are the final dimensions of your pcb?


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PostPosted: Fri Feb 03, 2012 1:01 am 
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captncraig wrote:
Looks great! What are the final dimensions of your pcb?


They are around 4.4"x5.0" basically takes up all the space in the cart.

Right now I'm just trying to figure out where I can get a small quantity run for $200 or less. It's proving to be a pain with the ass-ton of signals on the 4 layers since most deals have minimum specs that are pretty big.

If anyone has any ideas of manufactures let me know. So far advanced circuits is a no go. Imagineering is a possibility depending on some technicalities. I'm trying to see if I can route to Dorkbot's minimums right now...


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