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PostPosted: Fri Nov 02, 2012 5:06 pm 
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tepples wrote:
I don't know if it's a bug in NESICIDE or a bug in my test, but either way, it'd prevent Battletoads from running correctly.


Since I copied the mirroring setup from the buggy Verilog on the wiki, it could certainly be a bug. I will implement the behavior described not the Verilog. Look for a new release soon.


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PostPosted: Fri Nov 02, 2012 5:34 pm 
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tepples wrote:
I don't know if it's a bug in NESICIDE or a bug in my test, but either way, it'd prevent Battletoads from running correctly.


Ok think I got it matching the wiki behavior now. Download version 24 from the NESICIDE project page. Try it. Let me know. If it works I'll release it...it's got a few other fixes for other things.


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PostPosted: Fri Nov 02, 2012 6:08 pm 
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Findings:
  • The installer should offer to run the previous version's uninstaller instead of dumping the user back at the prompt.
  • Good news: Behavior for writing $80 then $01 matches what I expect (AA, AA, CC, F0).
  • Behavior for writing $01 then $80 will be added to the test later.


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PostPosted: Fri Nov 02, 2012 6:12 pm 
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tepples wrote:
Findings:
  • The installer should offer to run the previous version's uninstaller instead of dumping the user back at the prompt.
  • Good news: Behavior for writing $80 then $01 matches what I expect (AA, AA, CC, F0).
  • Behavior for writing $01 then $80 will be added to the test later.


I have hunted through Advanced Installer for an option to do just that but haven't found one yet. When I do you can bet I'll turn it on!


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PostPosted: Fri Nov 02, 2012 6:40 pm 
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Hint: http://www.advancedinstaller.com/user-guide/upgrades.html


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PostPosted: Sat Nov 03, 2012 5:43 pm 
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I implemented mapper 28 in Bizhawk to-day. It seems to work well enough, but there's only that one test rom.


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PostPosted: Sun Nov 04, 2012 12:32 am 
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tepples wrote:
If the registers are written in the order $80 then $01, then increasing bank modes from 00 to 03 are supposed to return AA, AA, CC, F0.


This is what I get on my cart. Sounds like AxROM mirroring works then since I'm getting 'AA' right?

cpow wrote:
Since I copied the mirroring setup from the buggy Verilog on the wiki, it could certainly be a bug. I will implement the behavior described not the Verilog. Look for a new release soon.


What differences are you seeing? I've read over the behavior several times now and I'm pretty sure it's set up correctly. But I've missed things in the past ;)

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PostPosted: Sun Nov 04, 2012 5:45 am 
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Perhaps it was copied from an old version of the Verilog.

I have been working on the test ROM, but I can only do so much while away from the house with my desktop PC that has NESICIDE on it, other than perhaps loading NESICIDE on someone else's PC, based on INL's revised Verilog or kevtris's untested Verilog. Hopefully thefox can get the PowerPak version working soon. I did manage to get the automated test to start running in FCEUX and display an error message.

I have a few questions about using NESICIDE as an IDE, which I'll bring up in the other topic.


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PostPosted: Sun Nov 04, 2012 7:57 am 
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infiniteneslives wrote:
Additionally thefox should be able to take my verilog and dump it into mapper #28 of power pak mappers to allow for additional testing. The one thing to keep in mind when he does that though is default/startup values my code doesn't actually cover that, it's a setting in the fitting properties of Xilinx webpack.

Can't you do this in Verilog? At least for my FPGA projects, it picks up the initialization values from Verilog automagically, i.e.
Code:
reg [5:0] prg_outer_bank = 6'hFF;   //sets PRG ROM A15-20

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PostPosted: Sun Nov 04, 2012 8:03 am 
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tepples wrote:
Perhaps it was copied from an old version of the Verilog.

Perhaps so. I haven't gone back to look at the verilog since I got it working.
tepples wrote:
I have been working on the test ROM, but I can only do so much while away from the house with my desktop PC that has NESICIDE on it, other than perhaps loading NESICIDE on someone else's PC, based on INL's revised Verilog or kevtris's untested Verilog. Hopefully thefox can get the PowerPak version working soon. I did manage to get the automated test to start running in FCEUX and display an error message.

Did you catch my note about unchecking the "bug icon" in the toolbar to disable some of the more intensive debuggers. Unfortunately it currently disables the breakpoint engine too but I'm thinking about leaving that in. If performance of the IDE is your main issue it'd be something to try.
tepples wrote:
I have a few questions about using NESICIDE as an IDE, which I'll bring up in the other topic.

Great! In my experience [both professional and private], user feedback always leads to a better end product.


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PostPosted: Sun Nov 04, 2012 9:47 am 
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thefox wrote:
Can't you do this in Verilog? At least for my FPGA projects, it picks up the initialization values from Verilog automagically, i.e.
Code:
reg [5:0] prg_outer_bank = 6'hFF;   //sets PRG ROM A15-20


Perhaps you can with the FPGA, From what I understand it won't work for me on the CPLD. If it's worked for you in the past I say go for it. I found online where it said you had use the flag 'defparam' to initialize in the code. This is all dependent on the compiler/synthesizer not necessarily verilog 'rules' as far as I know.

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PostPosted: Wed Nov 07, 2012 1:39 pm 
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tepples wrote:
I noticed that the nametable visualizer in NESICIDE reacts instantly when I press F8 to step to the next instruction. This is convenient; FCEUX's doesn't.


Doesnt this conflict conceptually with the idea of tying the nametable viewer update to a specific scanline? There would need to be a way to change the nametable viewer to refresh every time the debugger snaps, instead of at the specified scanline.


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PostPosted: Wed Nov 07, 2012 1:58 pm 
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zeromus wrote:
tepples wrote:
I noticed that the nametable visualizer in NESICIDE reacts instantly when I press F8 to step to the next instruction. This is convenient; FCEUX's doesn't.

Doesnt this conflict conceptually with the idea of tying the nametable viewer update to a specific scanline?

True, both behaviors can't be enabled at once, but each behavior has its own uses.

Quote:
There would need to be a way to change the nametable viewer to refresh every time the debugger snaps, instead of at the specified scanline.

For that, I'd recommend a radio button with options "Current" and "Scanline #".

Anyway, I'm working on adding tests for CHR RAM size (8K, 16K, or 32K) and tests to rule out a bunch of obscure misunderstandings of nametable mirroring that arose from an IRC discussion with kevtris. I had someone make me PowerPak mappers for both 8K and 32K versions based on kev's Verilog code.


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PostPosted: Sat Nov 10, 2012 8:00 pm 
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I've attached the new test ROM. Push Start to rich begin the automatic test.

PowerPak mapper based on kev's Verilog: Pass
NESICIDE: Pass until reset phase; emulator does not support soft reset
FCEUX SVN: Pass until reset phase; soft reset changes to last bank


Attachments:
test28-0.03.zip [39.94 KiB]
Downloaded 378 times
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 Post subject: PowerPak version
PostPosted: Sun Nov 11, 2012 8:30 am 
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thefox has given me the go-ahead through an IRC conversation to distribute PowerPak mapper files (MAP1C.MAP) based on the Verilog implementation by kevtris, which pass test version 0.03. The two versions differ in their CHR RAM size:

  • The 32K version of the mapper provides four 8192-byte pages of CHR RAM.
  • The 8K version of the mapper provides one 8192-byte page of CHR RAM.

To clarify (January 2017):
Well-behaved games should run fine with the 32K. A few games may require the 8K version due to having been tested only on the 8K or on emulators that behave the same way. If you're testing a game that you're developing, use the one that matches how your board connects CHR A14-13.


Attachments:
File comment: PowerPak mapper with 32k CHR RAM
MAP1C-kev-v4-32k.zip [18.37 KiB]
Downloaded 332 times
File comment: PowerPak mapper with 8k CHR RAM
MAP1C-kev-v4-8k.zip [18.36 KiB]
Downloaded 292 times
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