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PostPosted: Sun Dec 02, 2012 11:24 pm 
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Here's a project I've been working on for the last week or two. It's a normal NTSC NES (with composite PPU) with some hooks into an FPGA board. Result: Pixel perfect RGB output through VGA. At this point the project is pretty much done and seems to be working reliably, I've thrown a ton of games at it without problems.

The moire artifacts in the images were caused by the camera.

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PostPosted: Sun Dec 02, 2012 11:53 pm 
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Location: Estonia, Rapla city (50 and 60Hz compatible :P)
Pretty !

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PostPosted: Mon Dec 03, 2012 12:46 am 
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Awesome! Does it handle emphasis? Do you have a full 256x240 pixel buffer, or are you managing this with just one or two scanlines of memory? If the latter, how do you deal with the intermittently missing prerender pixel? What hardware is on your FPGA board?


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PostPosted: Mon Dec 03, 2012 4:57 am 
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Care to explain the technical details? NICE


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PostPosted: Mon Dec 03, 2012 7:43 am 
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Ignoring emphasis, it can be done by sampling the minimum level, maximum level, and phase over an entire pixel period and determining the intended palette entry from there.


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PostPosted: Mon Dec 03, 2012 8:03 am 
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Totally awesome, thefox! Looks gorgeous!


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PostPosted: Mon Dec 03, 2012 9:22 am 
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awesome :mrgreen:
will you be releasing details so people can (hopefully) build it?


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PostPosted: Mon Dec 03, 2012 10:04 am 
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Thanks for the comments.

lidnariq wrote:
Awesome! Does it handle emphasis? Do you have a full 256x240 pixel buffer, or are you managing this with just one or two scanlines of memory? If the latter, how do you deal with the intermittently missing prerender pixel? What hardware is on your FPGA board?

Emphasis is in the lookup table right now (9 bit index) so it works OK, I dumped the palette from Nintendulator. I used two scanline buffers. VGA timing is slightly off because NES only renders 240 scanlines and because of the missing dot, but my TV doesn't seem to care. I don't know if that's an exception or a common thing for displays.

The FPGA board is Altera DE2.

Jeroen wrote:
Care to explain the technical details? NICE

Maybe in the future. :)

keropi wrote:
awesome :mrgreen:
will you be releasing details so people can (hopefully) build it?

I don't know yet, right now it's not easy to build because it relies on DE2 (which costs $500, or about $250 for academic users). Also I have never designed a PCB before so there are lot of details that I don't know about when it comes to building a standalone version (like PCB manufacturing, board stuffing, level conversion, cheapest parts to use, etc).

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PostPosted: Mon Dec 03, 2012 10:23 am 
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My guess is that the ribbon to the NES intercepts the clock to the PPU and perhaps NMI so the external board can know when to sample video output and where it is in each pixel. Then it's just a matter of output levels at various points in the pixel and a lookup table, I imagine. I think that the original estimate of this being prohibitively expensive was on using just the composite output, nothing tapping into the PPU clock.


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PostPosted: Mon Dec 03, 2012 10:56 am 
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The PPU clock can be recovered from the sync and color burst. Perhaps the tapping is just to ensure an even cleaner clock signal.


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PostPosted: Mon Dec 03, 2012 11:32 am 
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Or like I said because it would be prohibitively expensive to implement the clock recovery in an FPGA (via oversampling? or a PLL that very quickly locks on?).


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PostPosted: Mon Dec 03, 2012 12:26 pm 
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thefox wrote:
VGA timing is slightly off because NES only renders 240 scanlines and because of the missing dot, but my TV doesn't seem to care. I don't know if that's an exception or a common thing for displays.
My LCD PC monitor is just fine with only receiving 524 total lines for VGA, but is really cranky about any jitter in its hsync-locked PLL pixel clock recovery circuit. Hence the question about the missing pixel :)

How many blocks does your design take?

blargg wrote:
Or like I said because it would be prohibitively expensive to implement the clock recovery in an FPGA (via oversampling? or a PLL that very quickly locks on?).
I never considered trying to do this without access to the PPU Clock, although I guess you might be able to use an 8x PLL from /RD or ALE...


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PostPosted: Mon Dec 03, 2012 12:40 pm 
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How is sync to color burst accomplished in an actual TV?


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PostPosted: Mon Dec 03, 2012 3:08 pm 
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After high-precision crystals became available, but before this was all done in digital, I believe it goes something like this:
* Retriggerable one-shot for the period after hsync ends
* One-shot output directly drives crystal with color burst as input
* After one-shot is done crystal is reconnected to itself


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PostPosted: Mon Dec 03, 2012 5:23 pm 
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So as I see it, a circuit with no connection to NES internals would involve a 6*CB crystal to lock to the color burst and derive the PPU clock from that.


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