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 Post subject: Multi-discrete mapper
PostPosted: Sun Oct 14, 2012 6:05 pm 
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I'm attaching my first attempt at a test ROM for the multicart mapper supporting multiple discrete logic mappers before I port the first volume of Action 53 to it. Compare its output to the output from this Python program. Once I have an emulator or PowerPak mapper that comes close to matching, I'll make an exhaustive automated test.

EDIT: removed defective test ROM


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 Post subject: Re: Streemerz bundle
PostPosted: Mon Oct 15, 2012 12:41 am 
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tepples wrote:
Compare its output to the output from this Python program.


I'm a little confused as to what I should be expecting to see/compare against.

I built things up tonight on the prototype, but am only looking at a blue screen at the moment. I checked and as I suspected things are not starting up with the last bank visible. A little late for debugging at the moment... I'll have to play around with it later.

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 Post subject: Re: Streemerz bundle
PostPosted: Mon Oct 15, 2012 5:54 am 
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infiniteneslives wrote:
I'm a little confused as to what I should be expecting to see/compare against.

I can explain it in detail later. Suffice it to say that FCEUX starts to run it.

Quote:
I built things up tonight on the prototype, but am only looking at a blue screen at the moment.

I don't remember writing any blue to the palette. The screen is supposed to be green on black.

Quote:
I checked and as I suspected things are not starting up with the last bank visible.

Did you get the error message to that effect, or did you figure it out some other way?


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 Post subject: Re: Streemerz bundle
PostPosted: Mon Oct 15, 2012 6:18 am 
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tepples wrote:
Quote:
I built things up tonight on the prototype, but am only looking at a blue screen at the moment.

I don't remember writing any blue to the palette. The screen is supposed to be green on black.

Quote:
I checked and as I suspected things are not starting up with the last bank visible.

Did you get the error message to that effect, or did you figure it out some other way?


I think it's just blue because nothing is happening in the eyes of the CPU. I checked with an oscope/volt meter. All the registers don't appear to be starting as set like I told them to. I didn't have time to look much deeper. I doubt it's much of an issue, I'll have to dig in more tonight to find out what's going on with the start up values. There are a few ways that are supposed to allow you to command how the registers to start up set/clear. I'll try the other methods and see what happens. Might have to make a few simple experiments.

Good to hear its alive and running in an emu already!

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 Post subject: Re: Streemerz bundle
PostPosted: Mon Oct 15, 2012 7:03 am 
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infiniteneslives wrote:
I think it's just blue because nothing is happening in the eyes of the CPU.

So in other words, your NES powers on with a blue backdrop in PPU $3F00.

Quote:
Good to hear its alive and running in an emu already!

Not quite. FCEUX is using its default behavior for unknown mappers, which appears to be loading the first bank into $8000 and the last bank into $C000. This is enough to get the test program running at least, displaying this:
Code:
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
1F 1F 1F 1F 1F 1F 1F 1F
1F 1F 1F 1F 1F 1F 1F 1F

That means bank $00 in $8000 and bank $1F in $C000, for all values of current bank (register $01) from $00 to $0F. I can trigger various other error messages ("fail: does not power on in last bank" and "fail: the ROM is winning bus conflicts") by configuring my builder to change the mapper and the number of copies of the non-last bank in the test ROM.


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 Post subject: Re: Streemerz bundle
PostPosted: Mon Oct 15, 2012 10:28 pm 
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tepples wrote:
infiniteneslives wrote:
I think it's just blue because nothing is happening in the eyes of the CPU.

So in other words, your NES powers on with a blue backdrop in PPU $3F00.


That's my guess.

So I figured out the start up value issue. Apparently Xilinx webpack likes to completely ignore the 'design goals and strategy' and requires the setting to be set individually for each step of the process. The compiler report revealed it's ignorance, I'm just glad I figured this out now. Should help out with power and speed/area goals as well.

Anyways, I checked it out and it still wasn't working (just blue screen) although things weren't always jammed up according to the old oscope. I did realize why I got mixed up between mode 2 and 3 yesterday... I didn't read the wiki close enough and actually coded modes 2 & 3 backwards.

I fixed the mix up but am still am only getting blue screen though. I'm guessing the issue is on my end somewhere though. Because I swaped up the reg select values 1<->3 so it should play a 256KB UOROM game upon start up (all my bits startup with a 1) when configured that way and it's not working... I think I just found another bug though. I now get randomly colored screens with paperboy 2 sitting in the board and register select values mixed up for testing/debugging. Exciting to see something besides blue :)

Based on all that looks like I'm still having issues somewhere. I'll have to comb through my code tomorrow and see if I can find anything else. A little to tired for that at the moment... If I don't see anything I'll just slowly hard code things into UOROM until it starts working then step my way back to the intended design.

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 Post subject: Re: Streemerz bundle
PostPosted: Tue Oct 16, 2012 4:17 am 
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Quote:
Good to hear its alive and running in an emu already!
Not quite. FCEUX is using its default behavior for unknown mappers, which appears to be loading the first bank into $8000 and the last bank into $C000. This is enough to get the test program running at least, displaying this:
Code:
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
1F 1F 1F 1F 1F 1F 1F 1F
1F 1F 1F 1F 1F 1F 1F 1F

That means bank $00 in $8000 and bank $1F in $C000, for all values of current bank (register $01) from $00 to $0F. I can trigger various other error messages ("fail: does not power on in last bank" and "fail: the ROM is winning bus conflicts") by configuring my builder to change the mapper and the number of copies of the non-last bank in the test ROM.


I am seeing that screen in NESICIDE. Now to finish it.


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PostPosted: Sun Oct 21, 2012 3:37 pm 
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So I've managed to get two different error screens I'm kinda at a loss right now. Randomly at power up I'll either get blue screen, error last prg bank not at $C000, or bus conflict error.

I'm pretty sure I'm avoiding bus conflicts... How are you sensing this exactly?

My CPLD is starting with the last bank in the proper location, but based on scope traces I've got something over writing that making it so the last bank isn't there anymore once it's time to access it is my guess.

Could you share the source or step through how it initializes the mapper and makes it's decisions on errors? (EDIT: forgot it was on the wiki vice download...) (EDIT2: I guess the wiki doesn't have the source I'm interested in seeing) I can keep chipping away at it but not being 100% certain the issue is with my mapper I don't know how much value there is trying to debug further from my end.

I have found a few things that were wrong though, so my implementation has been far from bug free. I'm guessing the issue is still from my end, but I'm having a hard time figuring out where to look without having a 'golden' reference yet...

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PostPosted: Sun Oct 21, 2012 5:46 pm 
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Each 16 KiB bank in this ROM has a 10-byte footer:
  • $FFF6: Constant $00
  • $FFF7: Constant $FF
  • $FFF8: Bank number
  • $FFF9: Nonzero if last bank; otherwise $00
  • $FFFA: NMI vector
  • $FFFC: Reset vector
  • $FFFE: IRQ vector

Bus conflict detection relies on $FFF6-$FFF9. But I may have already found a bug in my test. I'll post another copy with source after I do some more checks.

EDIT: I found the bug. I've attached the corrected ROM with source code.


Attachments:
test28.zip [30.92 KiB]
Downloaded 172 times
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PostPosted: Mon Oct 22, 2012 5:46 pm 
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infiniteneslives wrote:
I have found a few things that were wrong though, so my implementation has been far from bug free.

I noticed your verilog [on the wiki] doesn't match the python output. I was using your verilog for my code implementation. But then again I can't see how the python output matches the mapper description. I'm feeling a bit stupid.

Take the mode $3c outputs:

Code:
mode $3c, outer bank $2a
$8000 banks: 50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f
$C000 banks: 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55


The first row makes sense to me. The second row I don't see how it's $55. I can only come up with $50.


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PostPosted: Mon Oct 22, 2012 6:09 pm 
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I didn't write the Verilog. INL may have swapped modes 2 and 3; the intent was to have them ordered like MMC1.

I originally intended for the outer bank size to be ignored for addresses within the fixed bank. From the wiki description:
Quote:
When the fixed bank ($8000-$BFFF in mode 2 or $C000-$FFFF in mode 3) is accessed, it treats accesses to the fixed bank the same way as accesses in mode 0 with 32K: the outer bank bits are passed straight through. For example, this would allow the fixed $C000 bank in mode 3 128K to be set to 16K bank 7 (as in mapper 2) or 1, 3, or 5. In mode 2 128K, the fixed $8000 bank could be configured as 16K bank 0 (as in mapper 180) or 2, 4, or 6.

With the outer bank set to $2A, the 16K banks used by 32K mode are $54 and $55, and the top half of this is $55. More commonly for a ROM of his size, the outer bank would be set to $2F, which produces the expected UOROM-alike last bank in the fixed slot.


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PostPosted: Mon Oct 22, 2012 6:32 pm 
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tepples wrote:
Each 16 KiB bank in this ROM has a 10-byte footer:
  • $FFF6: Constant $00
  • $FFF7: Constant $FF
  • $FFF8: Bank number
  • $FFF9: Nonzero if last bank; otherwise $00
  • $FFFA: NMI vector
  • $FFFC: Reset vector
  • $FFFE: IRQ vector

Bus conflict detection relies on $FFF6-$FFF9. But I may have already found a bug in my test. I'll post another copy with source after I do some more checks.

EDIT: I found the bug. I've attached the corrected ROM with source code.


Ok this one's working for me but the fact that it has 32 banks and the python script assumes 64 banks [as far as I can tell] is throwing me off a bit.

EDIT: Just for fun I tried compiling it with NESICIDE:

Unresolved external `autorepeat' referenced in:
src/main.s(293)

I had to set USE_DAS to 1 in pads.s...


Last edited by cpow on Mon Oct 22, 2012 7:05 pm, edited 1 time in total.

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PostPosted: Mon Oct 22, 2012 6:36 pm 
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The bankdupe.py script in the build process can make up to 128 banks. I used 32 banks (4 Mbit) in the .NES file because that's the EPROM size that INL had on hand and the same size as the Streemerz bundle.

To fix calc_prg_bank() for a 4 Mbit ROM, change one of the first lines:
Code:
    outer_bank = (outer_bank << 1) & 0x1F


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PostPosted: Wed Oct 24, 2012 8:26 pm 
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tepples wrote:
The bankdupe.py script in the build process can make up to 128 banks. I used 32 banks (4 Mbit) in the .NES file because that's the EPROM size that INL had on hand and the same size as the Streemerz bundle.

To fix calc_prg_bank() for a 4 Mbit ROM, change one of the first lines:
Code:
    outer_bank = (outer_bank << 1) & 0x1F


I just pushed support for the PRG mapping and mirroring portions of mapper 28 to NESICIDE's gitorious repository. I will finish up the CHR mapping support and do a build at that point. My test28.nes output matches the python script.


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PostPosted: Wed Oct 24, 2012 10:47 pm 
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Okay it appears that bug you found and fixed up resolved some issues for me Tepples. I didn't change anything aside from the ROM and it now consistently boots up with a different error. Things are a lot more stable now and I've got somewhere to look so we're in good shape it would seem. I just need to track down the issue.

These are the current errors I've got:
Code:
msg_knownval_wrong:
  .byt "Fail!",LF
  .byt "$FFF6 and $FFF7 should have",LF
  .byt "$00 and $FF.  They don't.",LF
  .byt "A13 problem?",LF
msg_bus_conflict_and:
  .byt "Fail!",LF
  .byt "Writing $FF over a $00 value",LF
  .byt "in ROM did not swap in the",LF
  .byt "last bank.  Bus conflict?",


I've got to spend some more time looking over the source to figure out what might be going wrong. We're getting somewhere now though as the startup issues seem to be resolved.

I just end up with blank black screen after reset which would seem to be expected. I'm guessing this isn't handled in the code since my CPLD doesn't reset to last bank and everything as it does from power up. Correct me if I'm wrong but the end goal is to have console reset only reset the current selected game vice resetting back to the multicart menu, right? Without adding more circuitry/logic to the carts this is the only option really since I can only guarantee start up values of registers, and effectively can't sense reset.

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