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 Post subject: APU DAC curve
PostPosted: Tue Jul 16, 2013 12:54 am 
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http://wiki.nesdev.com/w/index.php/APU_Mixer

I have just gotten started on trying to test this behaviour on the hardware, and right away things don't seem to match well to the Triangle/Noise/DMC output; in particular the triangle seems to be louder than predicted by the first formula on that page. I need to think of proper ways to do this test before I proceed.

Does anyone have any insight as to how these curve formulae were developed? Who came up with them? Has anyone independently verified their accuracy?

Better yet, now that we have the visual 2A03 project and the nice decap images, has anyone analyzed the DACs in detail? Probably there's a lot you can't tell directly from the images, but at least their overall structure could be understood. (Sorry, at this time I do not have the skill to analyze these images myself.)

There's an interesting variation on that page that suggests the T/N/D is a nonlinear curve of the following digital mix: 3 * triangle + 2 * noise + dmc. That kind of thing could probably be determined true or untrue by visual analysis, couldn't it? Also, is it verified that the squares use a 5-bit DAC after adding together digitally?


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 Post subject: Re: APU DAC curve
PostPosted: Tue Jul 16, 2013 1:29 am 
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rainwarrior wrote:
Better yet, now that we have the visual 2A03 project and the nice decap images, has anyone analyzed the DACs in detail? Probably there's a lot you can't tell directly from the images, but at least their overall structure could be understood.
The DACs are enhancement n-type MOSFETs that connect Vcc to the pin with some constant resistance. Each of the 5 channels has its own DAC. Each next-most-significant bit in each DAC is made of twice as many MOSFETs as the previous, meaning half the resistance when on.
The nonlinearity comes from the use of a n-type MOSFETs rather than p-type. Because the on state resistance is a function of the output node's voltage, a higher instantaneous voltage causes all the MOSFETs to be less "on", so higher resistance, so quieter. I think that if p-type MOSFETs had been used with the external resistor, it would have been linear. Or, if they had used N-type MOSFETs sinking to ground, and had the external resistor connect to +5V. The exact curve will come down to both Vgs and Vds pinching off, but there's probably some kind of quadratic relation (given how MOSFETs work)

The resistance of each DAC is hard to tell; the exact sizing information in Visual2A03 has been processed. I'd tentatively guess that the noise LSB should be the same as the 2s bit of the DMC, and the triangle is louder, but it's hard to tell by exactly how much (The triangle channel's MOSFETs visually seem to be somewhere between ⅔ and ½ the length of the noise channel's MOSFETs, so ⅔ to ½ the on-state resistance)

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Also, is it verified that the squares use a 5-bit DAC after adding together digitally?
No, there's two 4-bit DACs inside. (Search visual2a03 for node "snd1", or transistor t10304)


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 Post subject: Re: APU DAC curve
PostPosted: Tue Jul 16, 2013 2:01 am 
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Okay, so if they are all separate DACs, are you suggesting that each DAC by itself is nonlinear to begin with? Or is there an additional nonlinearity resulting from how they are mixed together? (i.e. why does DMC affect triangle/noise, etc.)

i.e. my model might look like:
apu0 = apu0_mix(s0_dac(s0),s1_dac(s1))
apu1 = apu1_mix(t_dac(t),n_dac(n),dmc_dac(dmc))

I was wondering if the squares were digitally added, since the mixer formula adds them before doing anything else. ...not that I have any reason to trust the formula, I know it models some important characteristics of the hardware mix, but I don't have any empirical confirmation that it's correct yet (and it appears incorrect w.r.t. triangle in my very cursory initial tests).

Since they're not, that kind of dashes my hopes that it might have been a little easier to model. I suppose I'm just going to have to try to measure all possible outputs, then try to create a model that fits it well enough.


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 Post subject: Re: APU DAC curve
PostPosted: Tue Jul 16, 2013 2:53 am 
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I don't have the analog know-how here, but since it might be a handy reference, here's some images of the square channel mixer (from http://wiki.nesdev.com/w/index.php/Visu ... _.28DAC.29) and the triangle/noise/pcm mixer. I also included an image of the latter from the decap for comparison.

The yellow diffusion connects to the metal trace below (actually above), which goes directly to the output pin.

An interesting side note is that pcm_out0 uses a thicker gate as opposed to having less power attached to it, like for other bits.


Attachments:
tri_noi_pcm_mixer.png
tri_noi_pcm_mixer.png [ 42.75 KiB | Viewed 2062 times ]
Vis_da_conversion.png
Vis_da_conversion.png [ 15.91 KiB | Viewed 2067 times ]
tri_noi_pcm_mixer_decap.png
tri_noi_pcm_mixer_decap.png [ 243.76 KiB | Viewed 2067 times ]
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 Post subject: Re: APU DAC curve
PostPosted: Tue Jul 16, 2013 7:38 am 
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rainwarrior wrote:
Who came up with them?

The info comes from this doc: http://nesdev.com/apu_ref.txt (by blargg)

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 Post subject: Re: APU DAC curve
PostPosted: Tue Jul 16, 2013 1:14 pm 
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rainwarrior wrote:
Okay, so if they are all separate DACs, are you suggesting that each DAC by itself is nonlinear to begin with? Or is there an additional nonlinearity resulting from how they are mixed together? (i.e. why does DMC affect triangle/noise, etc.)
Yes, they are all slightly nonlinear. But the nonlinearity should only be a function of output voltage. i.e. It should be the case that you can add them linearly and then transform.

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then try to create a model that fits it well enough.
It should really just be the MOSFET constitutive law (per wikipedia)-
Either the gate is 0, and Vgs is 0 or negative, and so no current flows at all, or
Vgs=Vds=(5V-Vout)
and Ids = constants · (Vgs-Vth)²(1+λ(Vds-Vdssat)
And Vout = Ids·100Ω
I think λ is small enough we can basically not care about Vdssat, so this is quadratic instead of cubic?
In any case, throwing that all in Maxima, I end up with something of the form of Vout ∝ 1/√linearvalue


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 Post subject: Re: APU DAC curve
PostPosted: Tue Jul 16, 2013 10:05 pm 
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rainwarrior wrote:
Does anyone have any insight as to how these curve formulae were developed?

My guesses probably aren't too useful, but I'm going to guess that they were developed by making a test ROM that outputs different volume combinations from different channels, recording the output, then fitting a function based on the results.

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 Post subject: Re: APU DAC curve
PostPosted: Tue Jul 16, 2013 11:08 pm 
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Well, yes I presumed that much.

I was hoping for some specifics of the tests involved, and how much confidence there is in them, etc... Though chances are a lot of the details have been forgotten by now anyway. ;)

Anyhow, gives me some work to do for NSFPlay 2.4!


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 Post subject: Re: APU DAC curve
PostPosted: Fri Jul 19, 2013 10:27 am 
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I based it on the behavior of the circuit, including the external resistors on the PCB. As I remember, it was something non-linear due to the voltage divider set up. For data, I had channels output zero (tricky since the triangle doesn't power up at zero), then output values on a single channel only and observe the levels. I imagine that it might vary somewhat between NES units. I'm sure something better can be developed. It'd be a good starting point to examine the 2A03 circuit, then through measurement find the actual effective values of things in a particular NES, derive a model, then test it thoroughly on that NES. If that works, then measure the variation between NES units and form a typical set of values.


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