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PostPosted: Tue Apr 07, 2015 12:28 pm 
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The wiki mentions:

Code:
 CHR Mode is set by the following:
 
    $D000:  [SRNC CPPP]
      R,N = Relate to Mirroring (see mirroring section for details)
      S,P = Relate to PRG (see prg setup for details)
      C = CHR Mode
 
    $  :  [M.BH HHHH]
      M = Mirror CHR (very strange, see below)
      B = CHR Block mode (0=enabled, 1=disabled)
      H = CHR Block (when in block mode)


Is that a missing register number?


Last edited by zeroone on Fri Apr 10, 2015 12:00 pm, edited 3 times in total.

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 Post subject: Re: JY Company mapper
PostPosted: Tue Apr 07, 2015 1:05 pm 
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Somehow that got omitted from the original time when the information was copied to the wiki. Fixed.


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 Post subject: Re: JY Company mapper
PostPosted: Tue Apr 07, 2015 1:17 pm 
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Thanks.


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PostPosted: Tue Apr 07, 2015 1:20 pm 
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The D003 removal happened two more times on that page:
Code:
  $D000-  :   Control/Mode Regs
  $D004-D007:   mirror $D000- 


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PostPosted: Wed Apr 08, 2015 1:53 pm 
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Code:
Range, Mask:  $5000-FFFF, $F007
 
 
   $5000:        DIP switch         (read only)
   $5800-5801:   8*8->16 multiplier (read+write)
   $5803:        RAM                (read+write)
   $5804-5807:   ???                (possibly RAM)


I don't think that mask works for the $58XX registers.


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PostPosted: Wed Apr 08, 2015 3:14 pm 
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That is a very good question but I don't think we have better documentation than emulator source.

Nestopia uses a mask of 0xF803 for the registers in 0x5XXX, and a mask of 0xF007 for the registers above 0x8000.
FCEUX uses a mask of 0xFC03 for the registers at 0x580x and maps the same 0x5000 register at all twelve other locations. Also, FCEUX's source implies that what Disch called a "DIP switch" is actually a two bit #-of-resets counter.


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 Post subject: Re: JY Company mapper
PostPosted: Thu Apr 09, 2015 12:02 pm 
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I am having difficulty getting the mapper controlled nametables to work. For the unlicensed Super Mario World port (mapper 090), it appears to set the nametable registers to { 0, 1, 2, 3 }. That seems to suggest 4-screen VRAM. But, the wiki mentions that:

Code:
If the bits match, then NES internal NT RAM is used instead (either NTA or NTB, depending on bit 0 of the NT reg)


Since it seems to be configured to use internal NT RAM, why would it set the nametable registers to anything other than 0 and 1?

During testing, I put in a hack where I set the nametable registers to { 0, 0, 2, 2 } (a vertical arrangement / horizontal mirroring). That at least got the title screen displaying correctly. But, screens of the game still appeared glitched.

Edit: I noticed it says, "mapper 090 behaves as though N were always clear (0)". Meaning, advanced NT control is disabled. It is still unclear why it sets the NT registers at all since they should have no effect in that mode. Debugging reveals that it switches between horizontal and vertical mirroring. I'm still having difficulty getting the backgrounds to display correctly.

Edit 2: I think I solved all my issues. It was mainly problems related to the interrupts.


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PostPosted: Fri Dec 16, 2016 10:29 am 
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According to the Wiki:

Quote:
IRQs are triggered by any one of 4 sources:
1) CPU Cycles
2) A12 Rises
3) PPU Reads (which happen 170 times per active scanline)
4) CPU Writes (wtf, I know, but it's true)

I *think* the only method used by any games is the A12. CPU Cycles may also be used... and I really doubt
the other two are used anywhere.


Apparently, this is not the case. From GoodNES 3.14, try Astyanax.7z <Aladdin - Return of Jaffar, The (Unl) [!].nes> in Nintendulator. There is a small bug in Mapper090.cpp:

Code:
void   MAPINT   CPUWrite (int Bank, int Addr, int Val)
{
   if (IRQenabled && ((IRQmode & 0x3) == 2))
      IRQcount();
   _CPUWrite[Bank](Bank, Addr, Val);
}
int   MAPINT   PPURead (int Bank, int Addr)
{
   if (IRQenabled && ((IRQmode & 0x3) == 3))
      IRQcount();
   int result = _PPURead[Bank](Bank, Addr);
   if (MMC2Mode)
   {
      if (Bank == 3)
      {
         if ((Addr & 0x3F8) == 0x3D8)
            LatchState[0] = 0;
         else if ((Addr & 0x3F8) == 0x3E8)
            LatchState[0] = 2;
         else   return result;
         if ((BankMode & 0x18) == 0x08)
            SyncCHR();
      }
      else if (Bank == 7)
      {
         if ((Addr & 0x3F8) == 0x3D8)
            LatchState[1] = 4;
         else if ((Addr & 0x3F8) == 0x3E8)
            LatchState[1] = 6;
         else   return result;
         if ((BankMode & 0x18) == 0x08)
            SyncCHR();
      }
   }
   return result;
}


The test for IRQ modes 2 and 3 are mixed up.


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