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PostPosted: Fri Jul 24, 2015 1:47 pm 
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Joined: Mon Dec 29, 2014 1:46 pm
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Location: New York, NY
From http://nesdev.com/6502_cpu.txt :

Code:
  Relative addressing (BCC, BCS, BNE, BEQ, BPL, BMI, BVC, BVS)

        #   address  R/W description
       --- --------- --- ---------------------------------------------
        1     PC      R  fetch opcode, increment PC
        2     PC      R  fetch operand, increment PC
        3     PC      R  Fetch opcode of next instruction,
                         If branch is taken, add operand to PCL.
                         Otherwise increment PC.
        4+    PC*     R  Fetch opcode of next instruction.
                         Fix PCH. If it did not change, increment PC.
        5!    PC      R  Fetch opcode of next instruction,
                         increment PC.

       Notes: The opcode fetch of the next instruction is included to
              this diagram for illustration purposes. When determining
              real execution times, remember to subtract the last
              cycle.

              * The high byte of Program Counter (PCH) may be invalid
                at this time, i.e. it may be smaller or bigger by $100.

              + If branch is taken, this cycle will be executed.

              ! If branch occurs to different page, this cycle will be
                executed.


Does "Fetch opcode of next instruction" appear in those cycles due to pipelining? Meaning, does this timing actually reflect part of the next instruction?

Also, do those possible cycles cause interrupts to be delayed immediately after a branch? Or, is that an effect of something else?

Edit: This link answered all my questions. Thanks anyway.


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