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PostPosted: Tue Sep 29, 2015 5:03 pm 
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Out of curiosity, what method are you using to stitch the individual images?

The various chip scans done by Visual6502 seem pretty clean, and as I understand they were mostly "stitched automatically by Christian Sattler in the UK, using Autopano-sift-C and custom code".

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PostPosted: Tue Sep 29, 2015 9:11 pm 
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Visual 6502 stitches are probably done in the UK to work around the University of British Columbia's US patent on SIFT, the scale-invariant feature transform.


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PostPosted: Wed Sep 30, 2015 6:29 am 
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RP2C07 will be next. Very thanks to Rumata, who sent me this chip. Here is preferred decap order:
Code:
1. UA6538 - dendy/hybrid PPU ("UMC") (in progress)
2. RP2C07-0 - NES PAL PPU
3. UA6527P - dendy/hybrid CPU ("UMC")
4. TA-02NP - dendy/hybrid PPU ("TA")
5. TA-03NP1 - dendy/hybrid CPU ("TA")
6. RP2C02H-0 - Famicom AV PPU rev.H
7. RP2A03H - Famicom AV CPU rev.H

Famicom AV chips are in the end of list, because i think they are almost identical to "G"-revision already traced.
So, i missed only NES PAL CPU (RP2A07), because don't have it. :(


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PostPosted: Wed Sep 30, 2015 8:12 am 
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Thanks for the priority list.

Is there a plan to decap the unrevised 2A03 and 2C02 chips to see where the CPU/PPU changes between the recalled square-button Famicoms and the more common later revisions lie?


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PostPosted: Wed Sep 30, 2015 10:20 am 
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Siliconpr0n.org actually has a decapped (but not delayered) unrevised RP2A03, and quite a few differences have been identified, most notably the lack of looped noise (which is because the circuitry wasn't even there at all) and a bunch of disconnected mystery logic at the top-right corner of the chip (where the G revision has its giant test pattern).

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PostPosted: Wed Sep 30, 2015 10:57 am 
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I wonder what that big mystery blob is... It's still connected to the data bus, even if all the rest of the connections have been broken.


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PostPosted: Wed Sep 30, 2015 11:06 am 
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I attempted to trace it out (which was a bit tricky for the lower layers) and uploaded a simulator of it here - if you can figure it out, then by all means post your findings.

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PostPosted: Wed Sep 30, 2015 1:47 pm 
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This is a tangent...

It seems to be buggy; the data bus drivers's logic seems to be inverted from what it should be. Makes it hard to figure out what's going on... (Node 42 is "do not drive NES-internal data bus", but it's low (true/drivers enabled) whenever R/W=write or φ2=0. ... which is the wrong sense for the structure that exists.

Is there a convention for naming nodes? Especially in the cases of
- A = not B = not not C?
- D = not E and F = not E?

Anyway, I think it's an M2-based IRQ source... Node 20 appears indicates when all 24 latches have the same value. (Can't tell if 0 or 1). Nodes 75, 108, 141, 172, 209, 247, 278, 24, 76, 109, 142, 173, 210, 248, 279, 27, 77, 110, 143, 174, 211, 249, 280, and 307 appear to be ripple-carry outputs.

The 24-bit counter was intended to be both readable and writeable. Reads from $4017 seem to reload the counter. There seems to be some functionality to disable (or force?) reads from $4016 (what?).

Here's some nodenames: '/a0':317, '/a1':318, '+enable':276, 'NORenable_clk1':321, wraddr0:26, wraddr1:38, wraddr2:41, '+irq':843, '/irq_2':839, '/d0':858, '/d1':787, '/d2':672, '/d3':653, '/d4':583, '/d5':515, '/d6':452, '/d7':384, '_d0':290, '_d1':260, '_d2':224, '_d3':188, '_d4':147, '_d5':119, '_d6':85, '_d7':55, 'd0o':287, 'd1o':256, 'd2o':219, 'd3o':187, 'd4o':155, 'd5o':114, 'd6o':90, 'd7o':54, 'databus/oe':42, 'databus+oe':780, 'databus/oe_2':252, 'w/r':722, '/clk1':756, 'clk1_2':214, 'r/w_2':217, '/a0_2':239, 'a0_2':230, '/a1_2':688, 'a1_2':663, 'd0_pullup_ext':807, 'd0_pulldown_ext':300, wraddr3_2:203, wraddr2_2:202, wraddr1_2:204, wraddr0_2:205, '/wraddr3':30, '/wraddr2':39, '/wraddr1':35, '/wraddr0':32, 'wraddr0_2':852


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PostPosted: Thu Oct 01, 2015 12:22 pm 
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> So, i missed only NES PAL CPU (RP2A07), because don't have it.
I have a RP2A07 (and RP2C07-0) that you can get. Just PM me an address where to send it if you want (The pins are cut so I don't have much use for them anyway)

> The various chip scans done by Visual6502 seem pretty clean, and as I understand they were mostly "stitched automatically by Christian Sattler in the UK, using Autopano-sift-C and custom code".
I can forward an email to Christian if you want help with some stitching. I can't promise that he'll respond though :)

Btw, if anyone wants to run some tests on a square button famicom (to verify some behavior or whatever) I have one here with pcb revision 3 and revision less cpu & ppu.


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PostPosted: Thu Oct 01, 2015 1:37 pm 
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Thank you. See PM.


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PostPosted: Thu Oct 01, 2015 2:22 pm 
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Quietust wrote:
Out of curiosity, what method are you using to stitch the individual images?

The various chip scans done by Visual6502 seem pretty clean, and as I understand they were mostly "stitched automatically by Christian Sattler in the UK, using Autopano-sift-C and custom code".


Talked to them few years back, We are using similar stitching tech, but they use automated stage while I am still on manual.


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PostPosted: Fri Oct 02, 2015 9:02 am 
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barsmonster wrote:


Hopefully this one is final.

http://s.zeptobars.ru/UMC-UA6538-3.jpg
http://s.zeptobars.ru/UMC-UA6538-3-HD50.jpg
http://s.zeptobars.ru/UMC-UA6538-3-HD.jpg

Although, we might see errors only in the morning :-)


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PostPosted: Mon Oct 30, 2017 10:13 pm 
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Finally!, But this took me way too may years... :evil:
https://zeptobars.com/en/read/UMC-UA653 ... ntendo-PPU


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PostPosted: Mon Oct 30, 2017 11:23 pm 
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Anyway, original PAL NES PPU (RP2C07-0) will be next on priority list.

I want to ask community: what simply mappers need to decap high-priority,
maybe MMC3A, MMC3B and MMC3C?


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PostPosted: Mon Oct 30, 2017 11:47 pm 
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MMC5? :)


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