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PostPosted: Fri May 20, 2016 10:49 am 
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I have been contemplating porting Hex Frvr to the NES for a while, using 8x16 attributes.

8x16 attributes have the advantage that they can just be crammed into the two on-board nametables, making it famiclone-compatible. They're not quite practical to do just in discrete logic, but it does fit quite nicely into a GreenPAK.


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PostPosted: Mon May 23, 2016 6:16 pm 
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lidnariq wrote:
famiclone-compatible.
Is that because cart-edge CIRAM /CE isn't respected?


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PostPosted: Mon May 23, 2016 6:22 pm 
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Yeah, that.

It also imposes a nice tight constraint on not overdesigning.


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PostPosted: Sun May 29, 2016 12:36 pm 
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Oh, another thought: interrupts (or timed code) and raster effects are an easy way to get 16x8 attribute zones. Albeit at the cost of making the nametable layout suck as well.


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PostPosted: Sun May 29, 2016 2:45 pm 
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lidnariq wrote:
Oh, another thought: interrupts (or timed code) and raster effects are an easy way to get 16x8 attribute zones. Albeit at the cost of making the nametable layout suck as well.

The lower playfield in Klax uses this.


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PostPosted: Wed Jun 29, 2016 7:36 pm 
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It seems that non-minimal versions, including the "nice" arrangement in post 2, or the nicer arrangement of being in PPU_ are not workable on PowerPak (at least, not if one is using CHR chip, doing it onboard still works just fine…but then why not finish the ExRAM featureset with CPU-bus access?) because it does not interpose CHR data[7:0] or CHR address [9:3].


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PostPosted: Sat Jul 02, 2016 3:06 pm 
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On the other hand, neither does the Game Genie interpose CPU data. But does the PowerPak have bus conflict-prevention resistors?

In a less-inspired tone, even more "minimal" 8x8 attributes by using two bits of nametable would be in discrete range: two gated latches to store on NT fetch and output on AT fetch, decoding and some bus-conflict prevention circuitry- a 4x2:1 mux?
Code:
wire at = (& PPU_ADDR[9:6]);
wire CIRAM_CE = PPU_A13 & ~at;
wire LATCH_E = PPU_A13 & ~at & PPU_RD;
wire MUX_LATCH = PPU_A13 & at & PPU_RD;
//note I've not used the active lows

Fitting that logic onto two non-mux chips is left as an exercise for the reader.
Code:
wire CIRAM_CE_n = NOR (at,A13_n);
wire MUX_LATCH_SELECT = AND(at,NOR(A13_n,RD_n));//7421 7427
wire LATCH_E = NOR(at, A13_n, RD_n);

e: only possible with CHR-ROM.


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