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 Post subject: Timing of LYC==0
PostPosted: Tue Jul 26, 2016 4:05 am 
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Joined: Mon Jun 09, 2014 1:18 pm
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Location: Gothenburg, Sweden
Hi,

does anyone know whether the horizontal timing of the LYC interrupt at Y==0 is different to other rows?

It seems the timing, (the number of cycles before the row graphics is shown) is consistent for all rows but the first. At Y==0 the interrupt seems to occur somewhat earlier.

Cheers


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 Post subject: Re: Timing of LYC==0
PostPosted: Tue Jul 26, 2016 6:39 am 
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Joined: Sat Jun 27, 2015 1:09 pm
Posts: 68
I guess nobody truly knows,

What I've seen implemented in some emulators is that ly = 0 when the LCD is just turned on has 456 cycles and when it hits VBLANK, ly = 0 has that double timing behaviour (456 * 2).

I have it like that on my emu, but my interrupt code is a mess. Not really sure if theres a demo or game that relies on that specific quirck


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 Post subject: Re: Timing of LYC==0
PostPosted: Wed Jul 27, 2016 2:34 am 
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Joined: Mon Jun 09, 2014 1:18 pm
Posts: 11
Location: Gothenburg, Sweden
Thanks!

It seems LYC==0 is early by a time corresponding to about one scanline, compared to the other LYC interrupts.
This loop in the beginning of the interrupt at row zero puts it into phase:
Code:
        ld a,56
loop:
        dec a
        jr nz,loop


(cgb double speed)


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 Post subject: Re: Timing of LYC==0
PostPosted: Wed Jul 27, 2016 4:54 am 
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Joined: Sun Sep 19, 2004 11:12 pm
Posts: 19116
Location: NE Indiana, USA (NTSC)
Having it be zero during the equivalent of a "pre-render" line would make sense in a way to me.


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 Post subject: Re: Timing of LYC==0
PostPosted: Thu Aug 04, 2016 11:00 am 
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Joined: Thu Jun 16, 2016 11:53 am
Posts: 10
Wilbert Pol's fork of mooneye-gb has some tests for LY=0. If these are correct, the behavior is that LY=153 lasts for just 4 cycles, then becomes LY=0, even though the mode is still VBLANK. So LY=0 actually lasts for 452 + 456 cycles. But it looks like the LY=LYC interrupt for LY=0 doesn't fire exactly when LY becomes 0, but after a 4-cycle delay. Another interesting case that is likely related: it seems that if you write 153 to LYC on the cycle when LY becomes 0, the STAT interrupt will fire.


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