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Thank you. It works now. I had the ground to OE and OE on board to nothing.

Quick question here. I dont do SNES repros nor do i even own an SNES but how is an SNES considered 16 bit when its data bus for its mask roms are 8 bit?

Internally the SNES CPU perform math operations in 16 bit units.

The MC68000 inside the Mega Drive/Genesis have 16(sixteen) 32bit (thirty-two) registers yet it breaks 32bit calculations in two 16bit steps so that's why it's a 16 bit CPU.

And the Atari Jaguar has a 64-bit data bus DO THE MATH. But that's about the only 64-bit thing about it.

Ha! Yeah the jag was not as good as it should have been, but it is a badass looking system and some games were pretty cool.

I'm trying to learn all this stuff but I swear this is like learning a foreign language when you come into it w/a complete lack of any of it and I mean zero with a capital z. I have had many times now where I just had to walk away and come back days later.

My main thing right now is comprehending this.

The 74LS00 is used for address decoding. It's connection in the PCB is as follows:

ROM #1 /OE is enabled when SNES A21 is low and SNES ROM /OE is low.
ROM #2 /OE is enabled when SNES A21 is high and SNES ROM /OE is low.

I want to know what this low and high means. I am trying to understand the difference between a mad-1 and this 74LS00.

More so I have a game that doesn't work unless you run a wire from mask rom 2 on a SHVC-BJ0N-01 board hole a20 to pin 5 of the 74LS00 which is A21. However running it on a board SHVC-BJ1M-10 w/the mad 1 pin 13 "a21" needs to be lifted and a wire ran from it to the rom 2 a20.

Still trying to figure out what exactly is going on, I am now fairly sure it has to do w/the rom1 rom2 being enabled thing.

I'll try to define terms.


Low means the signal's voltage is close to ground (0 V). It represents a binary 0.
High means the signal's voltage is close to the supply voltage (+5V in the NES and Super NES). It represents a binary 1.
Active low means a signal is considered turned on when it is low. The name of an active low signal will begin with a slash, such as /OE.
/OE means an output enable that is active low. Chip enables on the NES and Super NES are active low more often than not.
/CE or /CS is a chip enable (also called chip select) signal that is active low. Both /CE and /OE need to be low for a chip to send data to the CPU. The difference between a chip enable and an output enable is that when chip enable is high, the chip uses less power, but the chip reacts faster to output enable going low than to chip enable going low.
A KiB (kibibyte) is 1024 bytes, or 2^10 bytes.
A MiB (mebibyte) is 1048576 bytes, or 2^20 bytes.
LoROM describes a memory mapping in Super NES Game Paks that does not connect A15 on the cart edge to the ROM. This means each 64 KiB of address space contains only 32 KiB of data. The other half is used for input and output ports and RAM inside the system.
HiROM describes a memory mapping in Super NES Game Paks that connects A15 on the cart edge to the ROM. This means each 64 KiB of address space contains 64 KiB of data. The terms LoROM and HiROM are distantly related to the canonical state of A22 when accessing ROM.

When SNES A21 is low, that means it's trying to read the first 2 MiB of address space. When SNES A21 is high, that means it's trying to read the second 2 MiB of address space. (2^21 = 2097152, and 2097152 bytes is 2 MiB.) On LoROM, each 2 MiB of address space contains 1 MB of data. On HiROM, each 2 MiB of address space contains 2 MiB of data.

Awesome, thanks for that.

Wow I just got this I think. Due to you writing "Snes A21". The snes system board is pulling information to A21 on the system board. That A21 was confusing the hell out of me, it never clicked to me to think outside of the game board/eproms.

So if I am reading this correctly by attaching a wire to hole 1 a20 since it is close to the +5v end "hole 36" that results in the signal for snes A21 to be high thus enabling rom #2. With no wire the system is trying to pull data from the low part of address space which since I split the rom, eprom 1 is the low part and eprom 2 is the high part! Since the information it needs is on eprom 2 snes a21 needs to be set high to get that information that is on eprom 2. Does that mean since a21 and a22 are also close, that running the wire to any of those said 3 said holes would achieve the same results?

What if you did a direct connection to hole 36 +5v would that be too much and cause damage?

If the rom is not split and a bigger chip was used this rewiring would be irrelevent?

Like I said before, the A lines are simply a binary representation of the physical memory address the CPU is attempting access to.

You trying to understand what is going on with that mindset (facing how the cartridge works as math equations) will have a big effect on how you see this "repro making" thing. Meaning that odd things will no longer surprise you or make you feel clueless. You will also have no difficulty understanding the different designs of cartridges and hardware.

My advice is you try to read a bit on boolean logic and binary math. It will help you a ton at understanding what you're doing.

Yeah, I sometimes get into the wrong thought process and nothing clicks. I actually read tepples post about 5 times, not to mention that rom 1 rom 2 like 30 times before and it never clicked to associate the system itself to what was going on.

I was stuck in the thought process of correlating everything on the game board to the roms/eproms. I will def. be looking up the Boolean logic and binary math. I did take some programming classes long ago but only for a year and it was more VB type stuff. It was all gui nothing real in depth on the component level. A little code here and there but it is very different.

Just wondering what I am missing here. I figured I would try doing 2 of these chips together but it didn't work lol.

I took a file 2.5MB and expanded it to 4MB (Lunar Expand). I then used wasabi to do just a plain 2MB split on the file, nothing else. I then programmed both 2MB parts onto two m27c160 chips. I rerouted pin 13 or OE for chip 2 to pin 11 on the 74ls00 decoder.

Mind you I use these chips to make 2MB games w/no problem. Just confused on why this didn't work. Do I need a multiplexor like a 74HCT139?

I was assuming the onboard decoder would be fine as I used a 2 mask rom pcb. Chip 1 is already routed properly for OE to 74ls00 pin 8.

I did notice chip 2 programmed super fast as compared to chip 1 which makes sense as it is really only 1/4 of the data as the rest is just padding.

OK, I just made Lufia 2 on two 27c160 chips. The game is 2560KB expanded to 4096KB and then split into two 2048KB files. I lifted pins 4, 12, 13 on mad chip. I wired pin 12 to a22, and pin 13 to a21, left pin 4 hanging. I then soldered pin 1 of mad to eprom 2 pin 13 OE and pin 16 of mad to eprom 1 pin 13 OE.

The game finally worked... somewhat lol. It now just resets. I cut the traces to mad pin 9 which is the reset and jumpered the broken connection but that didn't work. My thoughts are because I used 2 chips I still need a decoder. I was hoping I didn't but I think I do. Would I be correct in that assumption.

The other idea is the sram is causing copyright protection via the cic chip because splitting the file and rewiring the mad caused something it did not like.

I have an original Lufia 2 which uses a 1A3M-30 pcb which is exactly the same as the donor I used.

Why would you modify the MAD-1 for 2x27c160? The game does NOT exceed 4MB...

Lufia doesn't have a copy protection.

Because of what this says. It did not work at all w/out modding the mad-1. At least this way it does work, but resets after the 2nd splash screen.

I unfortunately never had a proper education on all this stuff so I am always learning the hard tedious way LOL.

Here is information I came across on both the 74LS00 and the Mad-1 decoder chips.

Based off that information the Mad-1 chip when used w/2 roms instead of one has to be rewired differently. It will not work w/2 roms the way they are connected via snes pcb's as those donors are configured at factory to accommodate 1 mask rom.

Unless this information is incorrect?



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