I have been testing hardware the entire yesterday and I've found and verified few things.
Things tested :
*SN76489AN in SC-3000
*315-5124 (SMS1 VDP)
*315-5246 (SMS2 VDP)
*315-5313-x (MD1 VDP)
*315-5476/5660/5700/5708/5960 (MD2 ASIC)
*315-6123 (Genesis 3 VA2 ASIC)
I would love to test out Sega SG-1000 II with 315-5066 chip which has VDP and PSG combined. It will be good to verify if it has vanilla PSG or what all other machines got, and also determine if the RGB output is same as SMS VDPs or different.
Freq of $000 acts as $400 on TI chip (MCLK / 32 / $400), producing lowest possible frequency. Decrement counter and then check for zero logic.
On Sega VDPs, freq of $000 acts same as $001, producing (MCLK / 32) output rate, highest possible frequency. Rest works exactly as on TI PSG. Freq of $000 is handled specially, which makes little sense from hardware perspective. I would have liked the extra low freq step, as the chip has very shit lower end freq range to begin with due to being clocked so high.
Noise phase is reset by frequency writes, volume writes have no effect. Noise always starts from low level. By spamming freq writes you can permanently keep noise output at low level.
Noise register is 15 bits on TI chip. Bits 0 and 1 are XORed and output to bit14 of left rotated register. Output is inversion of bit 0.
Upon phase reset, noise reg is reloaded with 100 0000 0000 0000.
Starting bit pattern of noise on TI chip : http://www.tmeeco.eu/SMS/TI%20PSG%20Noi ... ttern.flac
On Sega VDPs the register is 16 bits and bits 0 and 3 XORed and output to bit 15 of left rotated reg, output is still inversion of bit 0. Phase reset reloads noise reg with 1000 0000 0000 0000.
Starting bit pattern of noise on Sega VDP : http://www.tmeeco.eu/SMS/SEGA%20VDP%20P ... ttern.flac
Do notice the gap between start and first pulse, same thing also happens on hardware. Noise output is not instant, suggesting the way I do the noise register is correct.
Alternate noise mode produces 100/15 duty cycle square wave on TI chips and 100/16 duty cycle squares on Sega VDPs. Noise register is rotated left without any XOR magic and output is inversion of bit 0. The implication of this is that you need a new freq table to have noise in tune with tones on TI PSG, while on Sega VDPs noise is exactly 4 octaves lower allowing freq table to be reused.
Tone phase is not reset by either volume or frequency writes on TI chip or Sega VDPs. You can spam either to the chips and nothing happens as far as phase goes. Change applies immediately to current state. This has implications on PCM playback, only sane way to do it is by using highest possible frequency which then averages into something along the lines of DC level due to lowpass filters on the chip output path. This is also part of the reason why PCM playback is very quiet on actual hardware. If noise started at high level you could get reliable DC offset to exploit and get better results for PCM playback.
It is possible to detect TI PSG, as it has READY output which is connected to !WAIT line on Z80 in SC-3000 and if the chip is not ready, CPU is stalled until it is. You can spam writes to the chip and then determine if you have lagged behind or not. There is no such stall mechanism with Sega VDPs. Chip is able to accept one write every sample, I'm not right now sure if Sega VDP can accept data faster than TI chip or it misses the writes, I will have to do some explicit tests to determine that.
Outputs of TI chip behaves as expected, you have 4x log scaled channels that just get summed together. The output has tendency to oscillate at transitions from low to high and high to low, but that is fixed by placing a 150pF or smaller cap from Audio Out pin (9) to the Audio In / NC pin (7). TI chip is made of BJTs not MOS transistors.
Sega VDPs are made of NMOS transistors and require external current sinking resistor and this has some implications on what signals are like. The higher overall output level gets the less the resistor is able to sink current away and the more output flattens out, you do not get equal spacing of summed channels as current is running out. The resistor value used in SMS and MDs is 2.2Kohm, exception is SMS2 which uses an additional resistor to VCC on the output which really destroys 3 top levels of a channel causing totally messed up output :
this has 3 channels playing at the same time doing a volume ramp. The pic was taken a long time ago, my current digital scope is unable to show as clear result unfortunately as it has relatively low sample rate and things are full of aliasing artifacts. My other nice analog scope managed to develop dead tube. Normal, unmessed up output looks like this (just 2.2k resistor): http://www.tmeeco.eu/SMS/PSGgoodLevels.jpg
There is still some non linearity but it is much smaller. By using a lower value resistor (under 470ohm) you start getting output that starts reaching the ideal (like TI chip). NES for example uses 100ohm resistors on its audio outputs to get best possible linearity (albeit it still has problems due to varying DC offsets on different channels). TI, SMS1, SMS2 and MD chips all got differing DC offsets and peak-to-peak output levels. I will do accurate measuerements of all the levels in near future once I write out a good test program for that. It should be noted that while MD2 ASIC is CMOS, the PSG output is still NMOS based and requires sink resistor to function, while YM output is full CMOS based and will not function with sinking resistor in place (which are required for YM2612 which is NMOS).