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 Post subject: SNES clock change
PostPosted: Fri May 05, 2017 11:30 pm 
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Joined: Tue Feb 07, 2017 2:03 am
Posts: 248
So the SNES does
3.5
2.8
1.8 ish right.
And if you access the CPU regs or the Common RAM it goes at 1.8 but if you hit upper RAM or ROM it goes at 3.5 or 2.8...

Does it switch the clocks on the barrier or does it clock stretch to the clocks running at lower frequencies?
say you have a 3.5 to a 1.8 does it do
Code:
__    ____      __
  |__|    |____|  |__
or does the machine have
1.8      ____      ____
    ____|    |____|    |____
3.5   __   __   __   __   __
    _|  |_|  |_|  |_|  |_|
so when you switch from 3.5 to 1.8 on an odd clock it stretches
      _______      __   __   __
    _|       |____|  |_|  |_|
     ^ do 1.8 access here


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 Post subject: Re: SNES clock change
PostPosted: Sat May 06, 2017 1:11 am 
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Joined: Mon Jan 23, 2006 7:47 am
Posts: 70
The master clock always runs at 1890/88 = 21.47{72}MHz. The 5A22 contains (among other things) the 65c816 CPU and an address decoder, which translates the 65c816's bus address into SNES bus addresses, and determines the memory map region. The clock signal for the internal 65c816 is then simply held for 6, 8 or 12 master clock cycles while the rest of the 5A22 (e.g. DMA controller) and the system continues.


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 Post subject: Re: SNES clock change
PostPosted: Sat May 06, 2017 1:17 am 
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Joined: Sun Apr 13, 2008 11:12 am
Posts: 6272
Location: Seattle
In 6502 terms, the SNES's φ2 cycle is 3, 5, or 9 master clock cycles depending on the specific address accessed, while φ1 is always 3 master clock cycles.

(Ridiculous exception: DMA access is actually φ1=φ2=4 master clock cycles)


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 Post subject: Re: SNES clock change
PostPosted: Sat May 06, 2017 2:25 am 
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Joined: Fri Jul 04, 2014 9:31 pm
Posts: 781
Oziphantom wrote:
if you access the CPU regs or the Common RAM it goes at 1.8 but if you hit upper RAM or ROM it goes at 3.5 or 2.8

No.

Only the serial ports are XSlow (12 master clocks per byte, or 3 for φ1 and 9 for φ2). And you should never need to touch those unless you're using a nonstandard controller, or perhaps porting a NES game, because autopoll does it for you in the background.

All RAM in the system is Slow (φ2 = 5 master clocks), as is all ROM unless $420D is set to 1, in which case ROM in the upper half of the memory map ($8000-$FFFF in banks $80-$BF and $0000-$FFFF in banks $C0-$FF) is Fast (φ2 = 3 master clocks).

Internal CPU cycles (no bus access) and MMIO registers other than the controller ports are always Fast.

This is documented more precisely in Anomie's SNES Memory Mapping Doc:

Code:
The 'Speed' column indicates the memory access speed for that area of memory.
The SNES master clock runs at about 21MHz (probably as close to 1.89e9/88 Hz as
possible). Internal operation CPU cycles always take 6 master cycles. Fast
memory access cycles also take 6 master cycles, Slow memory access cycles take
8 master cycles, and XSlow memory access cycles take 12 master cycles.


  Banks  |  Addresses  | Speed | Mapping
---------+-------------+-------+---------
 $00-$3F | $0000-$1FFF | Slow  | Address Bus A + /WRAM (mirror $7E:0000-$1FFF)
         | $2000-$20FF | Fast  | Address Bus A
         | $2100-$21FF | Fast  | Address Bus B
         | $2200-$3FFF | Fast  | Address Bus A
         | $4000-$41FF | XSlow | Internal CPU registers (see Note 1 below)
         | $4200-$43FF | Fast  | Internal CPU registers (see Note 1 below)
         | $4400-$5FFF | Fast  | Address Bus A
         | $6000-$7FFF | Slow  | Address Bus A
         | $8000-$FFFF | Slow  | Address Bus A + /CART
---------+-------------+-------+---------
 $40-$7D | $0000-$FFFF | Slow  | Address Bus A + /CART
---------+-------------+-------+---------
 $7E-$7F | $0000-$FFFF | Slow  | Address Bus A + /WRAM
---------+-------------+-------+---------
 $80-$BF | $0000-$1FFF | Slow  | Address Bus A + /WRAM (mirror $7E:0000-$1FFF)
         | $2000-$20FF | Fast  | Address Bus A
         | $2100-$21FF | Fast  | Address Bus B
         | $2200-$3FFF | Fast  | Address Bus A
         | $4000-$41FF | XSlow | Internal CPU registers (see Note 1 below)
         | $4200-$43FF | Fast  | Internal CPU registers (see Note 1 below)
         | $4400-$5FFF | Fast  | Address Bus A
         | $6000-$7FFF | Slow  | Address Bus A
         | $8000-$FFFF | Note2 | Address Bus A + /CART
---------+-------------+-------+---------
 $C0-$FF | $0000-$FFFF | Note2 | Address Bus A + /CART

Note 1: The address for internal CPU registers may go out Address Bus A,
  however the CPU ignores the data bus. It is unknown whether the data bus
  is ignored for the whole memory region, or just for those addresses which
  are actually registers. It is also unknown whether CPU writes show up on
  the data bus or not. Current theory is that addresses and writes will show
  up, but reads may or may not, and the data bus is only ignored for those
  bits of those registers actually mapped (e.g., data bus is ignored for only
  bit 7 of $4211).

Note 2: If bit 0 of CPU register $420d is set, the speed is Fast, otherwise
  it is Slow.


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 Post subject: Re: SNES clock change
PostPosted: Sat May 06, 2017 4:05 am 
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Joined: Tue Feb 07, 2017 2:03 am
Posts: 248
Nice doc thanks for the link.

Ah keeping Phi1 the same simplifies it a bit, nice trick ;) So the clocks are
Code:
__    __    __    __    __    __    __    __
  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__| 3.5
 
_____    _____    _____    _____    _____    _____
     |__|     |__|     |__|     |__|     |__|     |__| 2.8
     
________    ________    ________    ________
        |__|        |__|        |__|        |__| 1.8


As we don't need to worry about 1.8 ;)

That still puts the 2.8 and 3.5 at odds every other cycle. But does the SNES keep the divides and switch or does it use have a loadable cycle counter so it doesn't need to stretch?


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 Post subject: Re: SNES clock change
PostPosted: Sat May 06, 2017 4:36 am 
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Joined: Mon Nov 10, 2008 3:09 pm
Posts: 429
Oziphantom wrote:
Nice doc thanks for the link.

Ah keeping Phi1 the same simplifies it a bit, nice trick ;) So the clocks are
Code:
__    __    __    __    __    __    __    __
  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__| 3.5
 
_____    _____    _____    _____    _____    _____
     |__|     |__|     |__|     |__|     |__|     |__| 2.8
     
________    ________    ________    ________
        |__|        |__|        |__|        |__| 1.8


As we don't need to worry about 1.8 ;)

That still puts the 2.8 and 3.5 at odds every other cycle. But does the SNES keep the divides and switch or does it use have a loadable cycle counter so it doesn't need to stretch?


The graph you've drawn is wrong, you've made φ2 6 clocks instead of 5. This is correct:

Code:
__    __    __    __    __    __    __    __
  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__| 3.5
 
____    ____    ____    ____    ____    ____
    |__|    |__|    |__|    |__|    |__|    |__| 2.8


There's no penalty when switching between slow and fast cycles, which is what I think you're asking? Each cycle of a single instruction can be (and frequently is) a different speed, and you just add the cycle lengths up to get the total time. However, there is a synchronization penalty of 2-8 master clocks when switching between instruction execution (variable length) and DMA (always 8 clocks per byte).


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 Post subject: Re: SNES clock change
PostPosted: Sat May 06, 2017 5:46 am 
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Joined: Tue Feb 07, 2017 2:03 am
Posts: 248
Awesome thanks.

Mostly just to see if there was a slide here or there as they can sometimes be useful and others a total PIA, and also to figure out how they did it.


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