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PostPosted: Tue Sep 05, 2017 9:54 pm 
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Are ROMs 1, 2, and 4, the same as the commercial ROMs? If so we can create an NES 2.0 image of this and finally get around to sussing out how to use byte 14 and 15 of NES 2.0 for extra ROM.


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PostPosted: Wed Sep 06, 2017 9:49 am 
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ROM is very similar to Moero!! Pro Yakyuu (Black) (J).nes, but there are a few random bytes different in first of PRG 16kB + bytes from 7fa8-7fea, which are FF in original, here are filled with some routine.
Other PRG and CHR are same.


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PostPosted: Wed Sep 06, 2017 10:03 am 
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Without those extra patched bytes (probably an added routine to write to 5000/5001) plus the call patch to get to that area, I cannot test this in an emulator :(

Do you have an .ips file patch which can be applied to the "Moero!! Pro Yakyuu (Black) (J).nes" version of the rom to turn it into this one, or something similar?

LN

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PostPosted: Wed Sep 06, 2017 10:12 am 
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Here:


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Moero Pro Yakyuu bootleg (apply over Moero!! Pro Yakyuu (Black) (J).nes).ips [104 Bytes]
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PostPosted: Wed Sep 06, 2017 8:16 pm 
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OK. Set it as mapper 86 submapper 1. Bit 1 is set on byte 14 of the NES2 header. The DPCM ROM is attached after the CHR. Interesting to get this UM5100 chip emulated...

Updated the NES 2.0 proposal information as well.


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Moero!! Pro Yakyuu (Black) (J) (Bootleg).nes [224.02 KiB]
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PostPosted: Sun Sep 10, 2017 3:27 pm 
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lidnariq: According to the game code it appears that you're right about the sample frequencies using $5000. (There are no instances of $5001 in code that I can see.)

It goes through a few routines where the normal $7000 functions play out. Almost immediately after the accumulator is OR'd with a value that sets bit 4 or bits 4 and 7; and stores to $5000. (ORA #$10 or ORA $#90) The correlation is that if the sample is a high-pitched sound like "crowd noise" it will set both bits 4 and 7. If it's speech it will just set bit 4. So, if bit 4 is set, it's "standard" speed. If bits 7 and 4 are set, it's double speed. I'm not certain what happens when none of the bits 7 through 4 are set..?


Last edited by B00daW on Sun Sep 10, 2017 3:37 pm, edited 1 time in total.

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PostPosted: Sun Sep 10, 2017 3:36 pm 
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Well, the hardware only has two speeds, regardless of whatever else is true.

Be careful; my estimates of 20 and 50 kHz were just back-of-the-envelope calculations.

Also, I misread the reverse-engineered schematic: the inverse of bit 7 is used, so it's "write with 128s bit high → pin is low → oscillator runs slower".


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PostPosted: Sun Sep 10, 2017 3:38 pm 
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I'm not so good at reading schematics just yet. I took a look at them though... I don't see instances of bit 4 for $5000?


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PostPosted: Sun Sep 10, 2017 3:41 pm 
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... Yes? That's exactly my point? Only bit 7 (the 128s bit) is used.


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PostPosted: Sun Sep 10, 2017 3:56 pm 
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Image
Image

Here is $1x and $9x being written to $5000.


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PostPosted: Sun Sep 10, 2017 4:02 pm 
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What exactly are you attempting to show me? I believed your initial summary (that it wrote with the $10s bit set).

The physical hardware cares about the 128s bit of the data bus. Or bit 7. Or whether the value is ≥$80 or not. However you want to phrase it.

It doesn't care about anything else. It isn't connected to anything else.


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