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 Post subject: Re: iNES Mapper 81
PostPosted: Thu Sep 07, 2017 1:29 pm 
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No one is claiming that this collector's copy is the only one in existence; it's just a rare game, much like all NTDEC original games. I posted the Kazzo dumping script so that some other collector could dump his copy and come forward and publicly release his dump. Having emulator support ready might increase the willingness to do so.


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 Post subject: Re: iNES Mapper 81
PostPosted: Thu Sep 07, 2017 1:57 pm 
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Location: NE Indiana, USA (NTSC)
But how can emulator support be ready if it cannot be tested?


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 Post subject: Re: iNES Mapper 81
PostPosted: Thu Sep 07, 2017 3:07 pm 
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Quote:
Although I'm not quite sure I understand the "deglitching" part

I said it at the beginning when noticed your post about registers ($6000) and the fact that this cartridge does not take M2 into account. So I thought of something that:
Image
This cap shorts quick spikes when occur during CPU address setup, so no strobe on register clock is generated.
But this cap is able to short only short spikes, but for NES it will work ecause all address lines (and ROMSEL) changing almost at the same time (with diference of few ns).
Now if u dump using kazzo, there is noticeable delay between address lines change because atmega sets them probably one bit at time (or one word at time), so this cap might be not enough and false strobe will be seen by register. And those caps on this PCB are indeed for CIC purpose.

But later I saw at this PCB in more details and saw only 1 latch so there is no possible of having 2 regs.

Quote:
I'm still waiting for krzysiobal for clarification of the D0...D3 instead of D3..D6 bits before I change the wiki article

Do you see any way how tracks from CART-45, CART-48, CART-48 can go to U1-11 (D0), U1-12 (D1), U1-13 (D2) and simulatenously go to U4-3, U4-4, U4-5, U4-6? Because I DONT unless there is third layer.
Image


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 Post subject: Re: iNES Mapper 81
PostPosted: Thu Sep 07, 2017 8:45 pm 
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But that's impossible, because the game definitely writes $00 at the title screen and $01 at game start to $FFE0/$FFE1, expecting a CHR-ROM switch to occur. It would have to write $00 and then $08 according to your schematic. (And the PRG-ROM content at $FFE0/$FFE1 matches what is written.)

Actually, I don't see how you know for sure that cartridge pins 46-43 must go to U1 and then to U4A, but that pins 49-47 cannot. You've drawn the red lines that way, but I don't see that from the original pictures. If one had another picture with U1 removed, it would clarify further, but I don't think that's something I can ask of the original cartridge owner.
tepples wrote:
But how can emulator support be ready if it cannot be tested?
Nintendulator support is ready, since I already have posted a tested source file (and can repost a compiled Mapper DLL file). And if another emulator implements it, I can test it.


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 Post subject: Re: iNES Mapper 81
PostPosted: Thu Sep 07, 2017 9:51 pm 
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You know .... I bet it latches the address bus.

It explains the bizarre topology between CPU D0-D2, PRG D0-D2, and 74'161 D0-D2. And why D3-D7 have their vias where they do. And why the default CNROM dumper script doesn't work.

If it's actually A~[1... .... .... PPCC]... then there are no relevant bus conflicts, either.


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 Post subject: Re: iNES Mapper 81
PostPosted: Thu Sep 07, 2017 10:01 pm 
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NewRisingSun wrote:
Actually, I don't see how you know for sure that cartridge pins 46-43 must go to U1 and then to U4A, but that pins 49-47 cannot. You've drawn the red lines that way, but I don't see that from the original pictures. If one had another picture with U1 removed, it would clarify further, but I don't think that's something I can ask of the original cartridge owner.
Topologically, we know the following:

Code:
[ unknown, underneath 74'161 ]
D0 D1 D2 D3
[ four total signals pass through here ]
[ unknown, underneath 27C512 ]
D0 D1 D2
   |
   |
D2 D1 D0
nothing this side


Draw non-crossing lines connecting all D0s, all D1s, all D2s; and do not have more than four lines visible in the region denoted with that constraint. This cannot be done.


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 Post subject: Re: iNES Mapper 81
PostPosted: Thu Sep 07, 2017 10:07 pm 
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Hm. There is at least one other NTDEC board (Asder 20-in-1) that does in fact latch the address rather than the data bus, so it wouldn't be out of character for them. So it would be actually:
Code:
void   MAPINT   Write8000 (int Bank, int Addr, int Val) {
   PRG = (Addr >>2) &3;
   CHR = Addr &3;
   Sync();
}
void   MAPINT   Reset (RESET_TYPE ResetType) {
   iNES_SetMirroring();
   for (int i=0x08; i<0x10; i++) EMU->SetCPUWriteHandler(i, Write8000);
   if (ResetType == RESET_HARD) PRG = CHR = 0;
   Sync();
}
This would at least provide working emulation. For the $6000 write one would still need to resort to the "compatibility write for a different PCB" explanation though. Maybe it's used on a 60-pin version of the game.


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 Post subject: Re: iNES Mapper 81
PostPosted: Thu Sep 07, 2017 10:13 pm 
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There's a pirate multicart in FCEUX (mapper 214) that's awfully close, but it banks 16 KiB PRG, doubled up, instead of UNROM-style PRG.

In Nintendulator's style, you should probably use an h_Latch object. In FCEUX, this belongs in addrlatch.cpp.


Register at $6000 could be equally easily excused as "changed in development" or "there to confuse reproduction-makers"


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 Post subject: Re: iNES Mapper 81
PostPosted: Thu Sep 07, 2017 11:19 pm 
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All right, if krzysiobal agrees with the plausibility of the address latch explanation, I'll update the wiki entry accordingly.


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 Post subject: Re: iNES Mapper 81
PostPosted: Fri Sep 08, 2017 3:30 am 
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Yea brilliant idea, a3-a0 can also be wired in this pcb. THat would also solve the problem why those two ground pads are orphaned - now they're also connected.

D3-D6:Image A0-D3: Image

BTW. The marking H/V on this PCB are wrong because this game wires VRAM-A10 to PPU-A11 (or maybe V stands for vertical arrangement, not vertical mirroring?)


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 Post subject: Re: iNES Mapper 81
PostPosted: Fri Sep 08, 2017 4:18 am 
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Thank-you very much, krzysiobal and lidnariq. I have updated the wiki entry accordingly, and updated my Nintendulator mapper source file as well, using the h_Latch object, as suggested. The Kazzo dumping script needs no modification, as it just straight-up replicates what the game writes, including the spurious $6000 write. If that 60-pin cartridge version I hypothesized about with a data latch at $6000 exists, the dumping script would dump that one as well. :P

Speaking of dumping scripts: I still don't understand why Kazzo's CNROM script, which just writes to $8000, does not fail due to bus conflicts --- are the Kazzo device's electrical characteristics such that the Kazzo byte always wins over the PRG ROM byte at $8000?

Now, to figure out how to submit to Nescartdb...

krzysiobal wrote:
maybe V stands for vertical arrangement, not vertical mirroring
Yes, the game is a vertical shooter. I suppose that with no access to official documentation, unlicensed Asian developers just realized that horizontal mirroring is appropriate for "vertical" and the other is suitable for "horizontal" scrolling and so used those words' initials.


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 Post subject: Re: iNES Mapper 81
PostPosted: Fri Sep 08, 2017 6:36 am 
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Location: NE Indiana, USA (NTSC)
NewRisingSun wrote:
krzysiobal wrote:
maybe V stands for vertical arrangement, not vertical mirroring
Yes, the game is a vertical shooter. I suppose that with no access to official documentation, unlicensed Asian developers just realized that horizontal mirroring is appropriate for "vertical" and the other is suitable for "horizontal" scrolling and so used those words' initials.

So did licensed Asian developers. H and V on Nintendo discrete boards stand for arrangement. I think only RetroUSB and RetroStage boards are marked using the mirroring convention.


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 Post subject: Re: iNES Mapper 81
PostPosted: Fri Sep 08, 2017 9:56 am 
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NewRisingSun wrote:
Speaking of dumping scripts: I still don't understand why Kazzo's CNROM script, which just writes to $8000, does not fail due to bus conflicts --- are the Kazzo device's electrical characteristics such that the Kazzo byte always wins over the PRG ROM byte at $8000?
Microcontrollers, such as the Atmega used by the Kazzo, often have comparatively ridiculously strong port drivers, capable of sourcing or sinking 10+mA while keeping the voltage on the pin within a volt of the corresponding rail.

In contrast, old NMOS designs (looking at the NMOS 68k datasheet) are often only rated 2 mA sinking and 400µA sourcing. The Kazzo assumes it can just completely overpower the ROMs on the cart, and it's almost always right.

It'd still be ideal if the dumper script took steps to prevent bus conflicts.


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 Post subject: Re: iNES Mapper 81
PostPosted: Fri Sep 08, 2017 10:07 am 
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Cut wires connecting microcontroller in kazzo to CPU data bus and put 200R serial resistors. Now ROM will always win bus conflict.


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 Post subject: Re: iNES Mapper 81
PostPosted: Fri Sep 08, 2017 1:32 pm 
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NewRisingSun wrote:
If that 60-pin cartridge version I hypothesized about with a data latch at $6000 exists, the dumping script would dump that one as well. :P

My guess would be that the $6000 writes are used for the unreleased Caltron 9 in 1 multi which does include this game and has a 1992 copyright on the menu screen. It was maybe done at the same time?

It was on sale a few months ago for a whopping 5 or 6k USD, BIN listing was put down because it wasn't available anymore. Here's the only PCB photo shown by the seller: Image


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