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PostPosted: Mon Jul 03, 2017 2:58 pm 
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Actually, the current info regarding RAMBO-1 IRQs is... wrong. I've updated the wiki (discussion page) with my suggestion of how it should work. Of course, I'm guessing and... it's working better than ever.

Is Kevtris around to analyse a RAMBO-1 board and its IRQ timing, like in the old days? He did even a RE of the mapper 90 IRQs!


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PostPosted: Fri Jul 07, 2017 3:24 pm 
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I believe I have figured out how RAMBO-1 IRQ timing works. 8-) :lol:

http://wiki.nesdev.com/w/index.php/Talk ... IRQ_timing


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PostPosted: Tue Nov 07, 2017 9:15 pm 
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Zepper wrote:
I believe I have figured out how RAMBO-1 IRQ timing works. 8-) :lol:

http://wiki.nesdev.com/w/index.php/Talk ... IRQ_timing


Is this still accurate information Zepper? Nestopia is very close to this IRQ in the undead implementation, and i would like to implement the rest of it if it is.

writes to $E001: irq_enable=true; IRQ acknowledge by CPU.

Nestopia was missing this in $E001 and i added it, but it does not seem like hard drivin works correctly with this. Can you confirm?


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PostPosted: Fri Nov 10, 2017 4:00 pm 
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What is the collateral effect?


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PostPosted: Fri Nov 10, 2017 6:20 pm 
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Well i need to do a little more testing but using that write to $E001: (irq_enable=true; IRQ acknowledge by CPU) makes hard drivin lose it's status bar before passing through the first gate.

At the moment, i am using Zxbdragon's implementation of code from when he added support for hard drivin. This code here:

Code:
// From dragon2snow
               if (reload)  {
                  if (latch < 1) {
                     count = latch + 1;
                  }
                  else {
                     count = latch + 2;
                  }
                  reload = false;
               }
               else if (!count) {
                  count = latch + 1;
               }
               
               count--;
               
               if (!count && enabled) {
                  /* wait one M2 cycle, then trigger IRQ */
                  return true;
               }
               
               return false;


After looking through what is posted on the talk link for the proper behavior, it is somewhat similar to that but not quite the same. One problem i am running into is not being able to outright add the line for irq_delay firing after 4 cycles due to the level of abstraction. In the hpp file for NstTengenRambo1.hpp i do see this though:

Code:
struct Irq
               {
                  Irq(Cpu&,Ppu&);

                  void Update();

                  enum
                  {
                     M2_CLOCK   = 4,
                     A12_FILTER = 16,
                     IRQ_DELAY  = 2,
                     SOURCE_PPU = 0x0,
                     SOURCE_CPU = 0x1,
                     SOURCE     = 0x1
                  };


So maybe i can just change that to 4 there after fixing the line of code above. One thing to note is martin's original code for this are used to be this:

Code:
bool Rambo1::Irq::Unit::Clock()
            {
               if (!reload)
               {
                  if (count)
                  {
                     return !--count && enabled;
                  }
                  else
                  {
                     count = latch;
                     return false;
                  }
               }
               else
               {
                  reload = false;
                  count = latch + 1;
                  return false;
               }


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PostPosted: Fri Nov 10, 2017 6:37 pm 
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Here's my current C code.
Code:
static inline void rambo1_clock(void)
{   
   if(MMC.irq_reset) {
      MMC.irq_counter = MMC.irq_latch+1;
      MMC.irq_reset = 0;
   } else if(0 == MMC.irq_counter) {
      MMC.irq_counter = MMC.irq_latch;
   } else {
      MMC.irq_counter--;
      if((0 == MMC.irq_counter) && MMC.irq_flag && (-1 == m64_irq)) {
      MMC.irq_reset = 1;
         m64_irq = 3; }
   }
}
/* runs at every CPU cycle.
 ppuflag is PPUADDR & $1000
 */
static void irq_rambo1(const unsigned int scanline, const unsigned int ppuflag)
{
   if(m64_irq > 0)
      m64_irq--;
   if(0 == m64_irq) {
      cpu_irqtrigger(TIRQ_MPR);
      m64_irq = -1;
   }
   if(0 != MMC.write) {
      if(0 == MMC.irq_timing) {
         rambo1_clock();
         MMC.irq_timing = 3;
      } else
         MMC.irq_timing--;
   } else {
      if( !ppu_is_rendering() ) { irq_latency = 8; return; }
      if(irq_latency > 0)
         irq_latency--;
      if(!irq_latency && ppuflag)
         rambo1_clock();
      if(ppuflag)
         irq_latency = 8;
   }
}


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PostPosted: Fri Nov 10, 2017 8:18 pm 
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I'll keep messing with it, thanks for posting that up zepper, but is this info still accurate?:

http://wiki.nesdev.com/w/index.php/Talk ... IRQ_timing


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PostPosted: Sat Nov 11, 2017 7:54 am 
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*Spitfire_NES* wrote:

It's a try-and-error result.


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