Is the following correct?
- 1. Between the CPU and the controller ports / expansion ports on both the NES and Famicom, all 2 x 5 input lines are inverted. Thus a 5V input from the controller pin / expansion port will be read by the CPU as a 0, and 0V will read as 1.
- 2. The outputs from the CPU ($4016 write D0-2) are not inverted. Sending a 1 from the CPU produces 5V output until $4016 is written again with a 0.
- 3. The CLK signal is normally 5V, but when the CPU reads $4016 or $4017 it becomes 0V while reading, and then returns to 5V once completed which will clock the shift register (low-to-high transition).
- 4. The expansion lines and the front controller port are both tied to the same inverting buffer, so it is not the case that one is inverted and the other is not.
Standard controller seems to say this stuff, now that I've kinda sorted it out and can follow what I'm reading but I just want to see if I understand this properly or not.