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PostPosted: Tue Jan 02, 2018 11:53 pm 
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Here's an odd question that I couldn't solve through searching.

My understanding is that the Super NES does not have its own memory map, and needs to communicate with an Adress Decoder (Mapper). Is this true? If not, what does the SNES memory map look like without a cart-based Lo/Hi/* ROM mappers?


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PostPosted: Wed Jan 03, 2018 12:31 am 
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It does. LO-ROM and HI-ROM are the SNES's map. Just the carts respond to or ignore certain address lines to get the mirroring/mapping they want.
Some carts us MAD-1 etc to make more modifications to the Map. but a stock SNES basically sees the RAM, PPU, APU only, and the rest is "open bus" for whatever the cart wants to put at the address.
Code:
$00-$3F    $0000-$1FFF    LowRAM, shadowed from bank $7E    (No ROM mapping)    $7E (First two pages of WRAM)
           $2000-$20FF    Unused                            (No ROM mapping)    $80-$BF
           $2100-$21FF    PPU1, APU, hardware registers     (No ROM mapping)    $80-$BF
           $2200-$2FFF    Unused                            (No ROM mapping)    $80-$BF
           $3000-$3FFF    DSP, SuperFX, hardware registers  (No ROM mapping)    $80-$BF
           $4000-$40FF    Old Style Joypad Registers        (No ROM mapping)    $80-$BF
           $4100-$41FF    Unused                            (No ROM mapping)    $80-$BF
           $4200-$44FF    DMA, PPU2, hardware registers     (No ROM mapping)    $80-$BF
           $4500-$5FFF    Unused                            (No ROM mapping)    $80-$BF
           $6000-$7FFF    RESERVED                          (No ROM mapping)    $80-$BF
I'm not sure if the Unused still generates a R/W signal for the cart edge of if they are just pure open bus.
7e&7F map to internal RAM. The rest is up to the cart.


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PostPosted: Wed Jan 03, 2018 1:35 am 
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Every read or write generates the /RD and /WR strobes. Every bus activity drives A0-A23.

The /ROMSEL signal on the card edge is literally just "low if ((A22 high or A15 high) and (A23-A17 not equal to 0x7E))". That's the closest thing you get to "the SNES's "native" memory map".

If you look at a plain 1A0N or 1J0N game you'll notice there's no address decoder IC.


Byuu previously talked about a "psychotic granularity" map which puts ROM in every single open-bus location, totaling almost 119mibit. (The only weird behavior comes from if you map things into $2184-$21FF on the A bus. You can mostly ignore that)


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PostPosted: Wed Jan 03, 2018 1:55 am 
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Fascinating. Would SRAM be usable in this case, or would that inherently need an address decoder to properly map it for the CPU? (I only ask because neither of the linked PCB info featured anything with battery-backed SRAM)


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PostPosted: Wed Jan 03, 2018 2:34 am 
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You would need something to make a "chip select" for the RAM, see http://snescentral.com/pcbboards.php?chip=SHVC-1A1B-05


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PostPosted: Wed Jan 03, 2018 7:52 am 
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anomie wrote:
As far as the SNES is concerned, this is the memory map.
"LoROM", "HiROM", and anything else is just the cart responding differently to the addresses placed on Address Bus A.

Note that the 65c816 inside the 5A22 has a very simple memory map and cares only about the zero page / direct bank, and the stack. The 5A22 translates the addresses and responds to offsets $4000..$43FF (if bank bit 6 is zero) or generates the chip's external pin signals (JPIO, JPCLK, JPOUT, REFRESH, SYSCK, /RAMSEL, /ROMSEL, /CPURD, /CPUWR, CA, /PARD, /PAWR, PA, D). Most of these go into the cartridge connector, and the cartridge can use any address decoder it wants to do anything it wants with the memory accesses.


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PostPosted: Thu Jan 11, 2018 12:12 pm 
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lidnariq wrote:
The /ROMSEL signal on the card edge is literally just "low if ((A22 high or A15 high) and (A23-A17 not equal to 0x7E))". That's the closest thing you get to "the SNES's "native" memory map".


That sounds interesting, where did you get that Information?


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PostPosted: Thu Jan 11, 2018 12:19 pm 
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It's already documented that /ROMSEL is low during

((Banks $00-$3F or $80-$BF) and address $8000-$FFFF) or (Banks $40-$7D or $C0-$FF)

I've separately looked at the signal on an oscilloscope and seen that it changes at the same time as the address bus, not the control signals.


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