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module MBC5
(
input not_reset,
input not_cs,
input not_wr,
input [7:0] data, // data bus value
input [3:0] address, // top 4 bits of address
output [8:0] out_rom_bank, // 9-bit ROM bank to use
output reg [3:0] ram_bank, // 4-bit RAM bank to use
output out_ram_enable // active low RAM enable
);
reg [8:0] rom_bank; // currently selected ROM bank
reg ram_enable; // is RAM enabled?
always@(posedge not_wr or negedge not_reset) begin // may need negedge instead?
if (!not_reset) begin
ram_enable <= 0;
rom_bank <= 1;
ram_bank <= 0;
end
else if(!not_wr) begin
case(address) // select based on top 4 bits of address
0, 1:
ram_enable <= data == 8'h0a;
2:
rom_bank[7:0] <= data;
3:
rom_bank[8] <= data[0];
4, 5:
ram_bank <= data[3:0];
// anything 6 or above ignored
endcase
end
end
// select fixed bank or switchable bank
assign out_rom_bank = address[2] ? rom_bank : 0;
// select external RAM at 0xA000 - 0xBFFF
assign out_ram_enable = !(ram_enable && address[3:1] == 3'b101);
endmodule