Problem with ADC and nestest

Discuss emulation of the Nintendo Entertainment System and Famicom.

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HastatusXXI
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Problem with ADC and nestest

Post by HastatusXXI » Sat Aug 25, 2018 12:01 pm

Hello.
I am testing my 6502 emulator and I am having some trouble with ADC. I am using this nestest log for this purpose: http://www.qmtpro.com/~nes/misc/nestest.log

Code: Select all

C966  A9 7F     LDA #$7F                        A:FF X:00 Y:00 P:E4 SP:FB CYC: 95
C968  69 80     ADC #$80                        A:7F X:00 Y:00 P:64 SP:FB CYC:101
C96A  10 0B     BPL $C977                       A:FF X:00 Y:00 P:A4 SP:FB CYC:107
According to this, C = 0 before ADC. Therefore, the operation is: A = $7F + $80. The result should be A = $FF. As the sign changes V flag should be 1. However, this log shows P = $A4, when I think it should be P = $E4. Why is this happening? Am I wrong?

lidnariq
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Re: Problem with ADC and nestest

Post by lidnariq » Sat Aug 25, 2018 12:09 pm

That adds -128 to +127. The result, -1, still fits in a signed 8 bit number, so oVerflow is not set.

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pubby
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Re: Problem with ADC and nestest

Post by pubby » Sat Aug 25, 2018 12:29 pm

Overflow flag isn't for sign changes. It's for if the result isn't represented correctly.

Here's a helpful page: http://www.righto.com/2012/12/the-6502- ... ained.html

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koitsu
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Re: Problem with ADC and nestest

Post by koitsu » Sat Aug 25, 2018 3:46 pm

adc/sbc have been discussed heavily over the years, and still remain the top struggle point for people writing 6502 cores. Here's reference material, including actual (very simple) code you can use to accomplish proper implementation: viewtopic.php?p=119626#p119626

P.S. -- Are you just writing a 6502 core, or are you writing a NES emulator? Thanks.

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tokumaru
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Re: Problem with ADC and nestest

Post by tokumaru » Sat Aug 25, 2018 9:38 pm

Signed numbers range from -128 to 127, so whenever the output is in that range, V should be clear. No addition of inputs with different signs can generate an invalid output (e.g. 0 + -128 = -128; 127 + -128 = -1), but when the inputs have the same sign, it's possible for the result to go below -128 or over 127 (e.g. -128 + -1 = -129; 127 + 1 = 128), resulting in invalid 8-bit 2's complement values. This means that the rule for the V flag is: if both inputs have the same sign AND the output has a different sign, set the V flag, otherwise, clear it.

BTW, this logic is for ADC, but when emulating the 6502, the simplest way to implement SBC is to reuse the ADC code but XOR the operand with 255. If I'm not mistaken, even the real chip implements SBC that way.

HastatusXXI
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Re: Problem with ADC and nestest

Post by HastatusXXI » Sun Aug 26, 2018 4:33 am

Thank you all for your answers. I was clearly wrong about the V flag. Now I can go on with the emulator.
koitsu wrote:adc/sbc have been discussed heavily over the years, and still remain the top struggle point for people writing 6502 cores. Here's reference material, including actual (very simple) code you can use to accomplish proper implementation: viewtopic.php?p=119626#p119626

P.S. -- Are you just writing a 6502 core, or are you writing a NES emulator? Thanks.
I am writing a NES emulator.

WedNESday
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Re: Problem with ADC and nestest

Post by WedNESday » Tue Dec 04, 2018 2:22 pm

Here is how I handle the V flag. I hope this helps you understand better how overflow works.

int temp;

temp = (char)A + (char)DataBus + C;

V = (temp < -128 || temp > 127);

Edits: Formatting.

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