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PostPosted: Fri Dec 14, 2018 2:17 pm 
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Joined: Sun Jun 12, 2011 12:06 pm
Posts: 498
Location: Poland
Game Genie controls PPU-A13, /ROMSEL and M2 of the slave-cartridge slot. All other pins are pass-through. Additionally CPU-D0..7 are connected to GameGenie via resistors as shown below. I believe those resistors are used to protect against bus conflicts when cartridge ROM hasn't stopped driving dat bus yet but Genie starts driving bus with data to be replaced.

Code:
   CONSOLE                                     SLAVE CART
                M2 ------------470R-------+--- M2
.-------------.                           |
| 4kB GENIE   |                           |
|  PRG-ROM /OE|--GND                      |
|          /CE|----------------------+    |
`-------------`                      |    |
                     .-------------. |    |
    VCC,GND,/RESET --| DIL48       |-+-|<-+
           /ROMSEL --| GALLOB      |-------- /ROMSEL
           PPU A13 --| GENIE       |-------- PPU A13
unused pins (22,30) -| CHIP        |
                     `-+-+-+-+-+-+-`
                    200R | | | | |   
         CPU D0-D7 ----+-|-|-|-|-|---------- CPU D0-D7
        CPU A0-A14 ------+-|-|-|-|---------- CPU A0-A14
          CPU R/W  --------+-|-|-|---------- CPU R/W 
         PPU D0-D7 ----------+-|-|---------- PPU D0-D7
           PPU /RD ------------+-|---------- PPU /RD
    PPU A2,4,5,6,7 --------------+---------- PPU A2,4,5,6,7
       other lines ------------------------- all other lines



My question is: what happends if Genie is going to replace data byte on $e000-$ffff when cartridge has its own RAM memory mapped at $6000-$7fff?
* Genie must drive the slave cart's /ROMSEL with 1, otherwise its ROM won't be disabled.
* Genie can't drive M2 with 0, otherwise its 4 kB PRG-ROM chip would be enabled
* But then slave cart's logic sees this cycle as read from $6000-$7fff and thus its RAM will drive data bus so Genie swapping won't succeed.

BTW. Any idea for those two unknown Genie's pins? Pin 30 is routed to C3, whose other side is GND (but C3 is not populated), pin 22 is not connected to anything.


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PostPosted: Fri Dec 14, 2018 8:21 pm 
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Location: Indianapolis
Good questions, I'm not sure. I was wondering about those unused pins myself. I kinda hoped it was a reset pin to get it back into the menu. Or maybe it's a disable switch like the later ones had. I haven't tried to do anything with it.

I'm not sure, but I thought the WRAM chips used normally weren't fast enough to start outputting data during the M2 glitch.

Game Genie also has those comparison bytes also, won't replace data unless it matches. I'm pretty sure every code for a PRG-switching mapper game was supplied with comparison bytes.


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PostPosted: Sat Dec 15, 2018 4:38 am 
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Joined: Sun Jun 12, 2011 12:06 pm
Posts: 498
Location: Poland
Code:
I'm not sure, but I thought the WRAM chips used normally weren't fast enough to start outputting data during the M2 glitch.

Game Genie also has those comparison bytes also, won't replace data unless it matches. I'm pretty sure every code for a PRG-switching mapper game was supplied with comparison bytes.

M2 glitch is not source of problem. When Genie sees correct matching data at $e000-$ffff (probably middle of the CPU cycle), Genie replaces it and drives CART-/ROMSEL high. At this time cart's logic sees access to $6000-#7fff and enables RAM (which is enabled until end of the cycle, that is until M2 goes low).
But for the rest of the cycle RAM will drive data bus, overriding the data that Genie is driving, causing the replaced value to be invalid.

For the same reason, MMC5 games with Exrom enabled in 00/01 mode will corrupt Genie replacement at $dc00-$dfff though I think that MMC5 games will make more trouble cause MMC5 is utilizing PPU /A13 rather than A13.
After Genie's & MMC5 bootup, MMC5 is in Nametable-Fill-Byte mode (for all four nametables) and so for $2000-$2fff it will output $FF, ignoring Genie's writes to nametable, causing Genie screen to be unreadable.


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PostPosted: Sat Jan 12, 2019 7:52 pm 
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Joined: Sun Jun 12, 2011 12:06 pm
Posts: 498
Location: Poland
I bought my first GG but I got blob instead and I'm disappointed ;'(

Image Image Image

Chip pinout of the blob is following:
Code:
              .---V---.
      CPU-D0  |01   48| VCC
      CPU-D1  |02   47| CPU-!ROMSEL
      CPU-D2  |03   46| CART-!ROMSEL
      CPU-D3  |04   45| PPU-A7     
      CPU-D4  |05   44| CART-PPU-A13
      CPU-D5  |06   43| PPU-A13     
      CPU-D6  |07   42| PPU-D7     
      CPU-D7  |08   41| PPU-D6
     CPU-A14  |09   40| PPU-D5
     CPU-A13  |10   39| PPU-D4
     CPU-A12  |11   38| GND         
     CART-M2  |12   37| !RESET     
      CPU-M2  |13   36| PPU-D3     
     CPU-A11  |14   35| PPU-D2     
     CPU-A10  |15   34| PPU-D1     
      CPU-A9  |16   33| PPU-D0     
      CPU-A8  |17   32| PPU-A2 
      CPU-A7  |18   31| PPU-A4     
      CPU-A6  |19   30| PPU-A5     
      CPU-A5  |20   29| PPU-A6     
      CPU-A4  |21   28| PPU-!RD     
      CPU-A3  |22   27| CPU-R/!W   
      CPU-A2  |23   26| CPU-A0     
         GND  |24   25| CPU-A1
              '-------'


Pin 38 (GND) is internally connected to the GND at 24.


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PostPosted: Sat Jan 12, 2019 8:06 pm 
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Joined: Sun Apr 13, 2008 11:12 am
Posts: 8391
Location: Seattle
Huh. The pin order isn't anything more than vaguely the same as the DIP48 version.


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