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PostPosted: Fri Jun 28, 2019 5:21 pm 
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Joined: Sun Apr 13, 2008 11:12 am
Posts: 8572
Location: Seattle
As far as I know, 30ns is a good ballpark for the propagation delay through the 74'139 inside the NES itself that causes this race.

I'll note that Nintendo's discrete logic mappers, such as UNROM (3), CNROM (2), and ANROM (7), just use a 74'161 with R/W connected to '161./LOAD and /ROMSEL connected to ↑CLOCK.


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PostPosted: Wed Jul 03, 2019 3:24 pm 
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Joined: Tue Jan 23, 2018 11:19 pm
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I changed my experiment to continuously sample CPU R/~W after CPU ~ROMSEL falls. It mostly simulates asynchronous SRAM as far as the R/~W line goes, but only for 220ns. After that it ignores R/~W until the next falling edge of ~ROMSEL, when it offers another window of 220ns.

Seems to work: I can read the value sent to the ROM space and I don't get spurious reads--that I can tell. I'll do more rigorous tests later.

Thanks, lidnariq! Very helpful info.


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