Boot routine/ bank selection?

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VIP Quality Post
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Boot routine/ bank selection?

Post by VIP Quality Post » Sun Mar 01, 2020 5:52 pm

So, I finally finished getting around to making some repro boards. However, I can't get the prototype boards to work. I hooked it all up to my logic analyzer and I am seeing some strange things that I am hoping someone can help me understand.

When the SNES boots, it does some CPU things for about 24 cycles, and then it starts polling the address bus. What I don't understand is the bank behavior. I will let it run for a few minutes, but the bank never switches off 0x40. The addresses move around like they're looking for data, but it just looks like gibberish to me. The WR/RD lines never get pulled down, so it's never pulling data from the cart, either. I was thinking that maybe the supercic I put in was programmed wrong, but if I check the status pin (referenced from the readme included with the code) it is high, indicating that it is properly talking with the lock inside, and also the reset pin is never pulled low, so it's not holding the CPU/PPU hostage.

If I pop my EEPROM back in my programmer, I can verify all the code with what was supposed to be programmed, and it seems to be all on there correctly. My SNES plays first party games just fine, so I can't see any issue with the SNES itself or the cart connector.

If you check the SNES dev manual CPU memory map, this bank (0x40) is the start of the ROM region, so I would expect to see /RD or /CART (probably both) pulled low, but they don't ever seem to. I'm not sure where to start troubleshooting what this problem could be. Here's the map from the manual:
map.PNG
In my logic analyzer picture: the labels are self explanatory. The last row is /WR /RD /CART from left to right. The cycles you can see in the picture are right after the start routine, or whatever is happening when the SNES boots.
snes.jpg

lidnariq
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Re: Boot routine/ bank selection?

Post by lidnariq » Sun Mar 01, 2020 6:11 pm

The 65816 in the SNES, like the 6502, is supposed to start out of reset by reading the two bytes at $00FFFC and $00FFFD and starting execution at that address, still in bank $00. If you're seeing something else, you've either got a wiring problem or a damaged SNES...

VIP Quality Post
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Re: Boot routine/ bank selection?

Post by VIP Quality Post » Sun Mar 01, 2020 6:58 pm

I went back and rechecked my connections. I had some mixed up connections which was why I was getting $3FFC and $43FFD- I have $FFFC and $FFFD now. But the bank is still stuck on $40, so there is something going on with BA6. But at least the reset signal is right. I'm going to check on it more and update when I find what the problem is.

edit: I had a wire shorted, BA6 reads fine now. But the screen still shows nothing. Further look shows the address bus rolling over every ~20 cycles $FFFE, $FFFF, $0000, $0001. Not sure why this is happening but taking a read through the dev manual again
Last edited by VIP Quality Post on Sun Mar 01, 2020 7:43 pm, edited 1 time in total.

lidnariq
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Re: Boot routine/ bank selection?

Post by lidnariq » Sun Mar 01, 2020 7:36 pm

I think it very unlikely, but you're not confusing the "B" address bus (on the extra pins on the cartridge) with the "b"ank pins of the primary address bus, right?

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Re: Boot routine/ bank selection?

Post by VIP Quality Post » Sun Mar 01, 2020 7:43 pm

No, I'm using A16-A23 as the bank pins.

lidnariq
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Re: Boot routine/ bank selection?

Post by lidnariq » Sun Mar 01, 2020 7:47 pm

VIP Quality Post wrote:
Sun Mar 01, 2020 6:58 pm
edit: I had a wire shorted, BA6 reads fine now. But the screen still shows nothing. Further look shows the address bus rolling over every ~20 cycles $FFFE, $FFFF, $0000, $0001. Not sure why this is happening but taking a read through the dev manual again
$FFFE,$FFFF are the emulation-mode IRQ/BRK vector. Since you see 0000 and 0001 after FFFE, FFFF, you went off the rails somewhere and then got in a BRK→jump to invalid vector in RAM, execute from RAM until you find another BRK instruction.

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Re: Boot routine/ bank selection?

Post by VIP Quality Post » Sun Mar 01, 2020 8:00 pm

I ctrl-F'd "emulation" in the dev manual, I don't see anything about this. Is there somewhere I can read more about it?
I looked up the 55 that's sitting on the data bus, and that looks like opcode for EOR, not sure if that's relevant.
I also found the section on the reset vector in the manual. I see the $FFFC and $FFFD addresses, but then it's noted that the CPU should write 8F to $2100 register. Am I not seeing this because it's a register and isn't external or is there some other reason?
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VIP Quality Post
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Re: Boot routine/ bank selection?

Post by VIP Quality Post » Sun Mar 01, 2020 8:01 pm

Oop! The emulation mode is for the processor for 65C05, right?

lidnariq
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Re: Boot routine/ bank selection?

Post by lidnariq » Sun Mar 01, 2020 8:05 pm

Yes, for the 65816. When the 65816 boots, it boots in emulation (CMOS 65C02) mode, and starts executing &c &c. If you'd gotten as far as switching into native mode, you'd instead have seen it fetch the bytes at $FFEE and $FFEF instead, when it executed the BRK instruction.

Doesn't really matter what's keeping you in this loop, just that it's wrong and you need to find where things went off the rails to fix it. Are you using someone else's initialization code? I used Tepples's and would recommend just using his verbatim.

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Re: Boot routine/ bank selection?

Post by VIP Quality Post » Sun Mar 01, 2020 8:10 pm

I have some code but since I was just trying to test the boards, I programmed a pre-existing game. Since I got the ROM dump from a working game, I'm really confused why it's not happy during startup.

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Re: Boot routine/ bank selection?

Post by VIP Quality Post » Sun Mar 01, 2020 9:18 pm

The thing that's really stumping me is that it's not even trying to read the ROM for initialization, it's never pulling RD low. I can't seem to find any specific information on what the CPU is supposed to do between the reset vector and when it looks for code to read from the ROM, which is where it's failing now. Could it be that some hardware I'm using is dragging down a line the CPU needs for booting or something?

lidnariq
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Re: Boot routine/ bank selection?

Post by lidnariq » Sun Mar 01, 2020 9:50 pm

You've got something electrically wrong, yes. The first several cycles are nonsense reads from the stack, followed by reading from $00FFFC and $00FFFD. Several years ago, Poot36 used some old HP logic analyzer like yours, and you can compare their power-on trace to yours.

Oziphantom
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Re: Boot routine/ bank selection?

Post by Oziphantom » Mon Mar 02, 2020 1:07 am

The 65XX boot sequence is

Fetch FFFC -> PC LO
Fetch FFFD -> PC HI
Fetch PC

that is the whole sequence

so your cart is either not reading 00FFFC/D or reading it properly. its R/_W so for READ the line will be high, the SNES will never pull the R/_W lo for reading from ROM. or at least it shouldn't.

As you had issues with the address pins, I would double check the data pins as well. You can open the ROM in a hex editor and see what values it should read at those locations and make sure your logs match.

lidnariq
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Re: Boot routine/ bank selection?

Post by lidnariq » Mon Mar 02, 2020 1:23 am

Oziphantom wrote:
Mon Mar 02, 2020 1:07 am
its R/_W so for READ the line will be high, the SNES will never pull the R/_W lo for reading from ROM. or at least it shouldn't.
SNES has /RD, /WR, and φ2 outputs, but no R/W.

nocash
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Re: Boot routine/ bank selection?

Post by nocash » Mon Mar 02, 2020 1:36 am

I am almost sure that the CPU stores a dummy return address on stack upon RESET, similar as IRQ/NMI/BRKk handlers do.

What is that talk about a pin with merged RD/WR or WR/RD signals? The SNES cart edge connector does only have separate pins for /RD and /WR.

Yes, there seems to be a R/W pin on the CPU, but it isn't connected anywhere, and I can't imagine how (or why) somebody could end up with logic analyzer wired to that CPU pin... at least not when building a cartridge.
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